Add documentation page indicating existence of prefetchers

ucb-bar · Jun 8, 2023 · 4aa3a4c · 4aa3a4c
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diff --git a/docs/Generators/Prefetchers.rst b/docs/Generators/Prefetchers.rst
@@ -0,0 +1,9 @@
+Prefetchers
+====================================
+
+The BAR-fetchers libraryis a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocketchip SoCs.
+This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers.
+
+Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus.
+
+An example configuration using prefetchers is found in the ``PrefetchingRocketConfig``
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
@@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building
    NVDLA
    Sodor
    Mempress
+   Prefetchers
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
@@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsp-utils`,
      gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-     constellation, mempress)
+     constellation, mempress, barf)
 @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
    .settings(libraryDependencies ++= rocketLibDeps.value)
    .settings(commonSettings)
-Original file line number
+Diff line change
@@ Expand Up @@
        NVDLA
        Sodor
        Mempress
+       Prefetchers