Prefetching config should use non-blocking L1D$

ucb-bar · Jun 12, 2023 · 4db4b22 · 4db4b22
1 parent 3e6e68a
commit 4db4b22
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/generators/bar-fetchers b/generators/bar-fetchers
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -130,7 +130,8 @@ class CustomIOChipTopRocketConfig extends Config(
 class PrefetchingRocketConfig extends Config(
   new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++   // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$
   new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++             // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2
-  new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2
+  new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2
   new chipyard.config.WithTilePrefetchers ++                                           // add TL prefetchers between tiles and the sbus
+  new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++                           // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                               // single rocket-core
   new chipyard.config.AbstractConfig)
+6 −1		README.md
+1 −0		src/main/scala/HellaCachePrefetcher.scala