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Bump FireSim
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@abejgonzalez
abejgonzalez committed Aug 20, 2024
1 parent 31c75c1 commit 6fd75a3
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2 changes: 1 addition & 1 deletion sims/firesim
Submodule firesim updated 71 files
+1 −1 docs/Advanced-Usage/FireAxe-Partitioning-onto-Multiple-FPGAs/Running-Exact-Mode-Simulations.rst
+3 −3 docs/Advanced-Usage/FireAxe-Partitioning-onto-Multiple-FPGAs/Running-Fast-Mode-Simulations.rst
+1 −1 docs/Advanced-Usage/FireAxe-Partitioning-onto-Multiple-FPGAs/Running-NoC-Partition-Mode-Simulations.rst
+298 −62 docs/Golden-Gate/Bridge-Walkthrough.rst
+13 −13 docs/Golden-Gate/Bridges.rst
+2 −7 sim/firesim-lib/src/main/scala/Nasti.scala
+1 −1 sim/firesim-lib/src/main/scala/bridgeutils/Bridge.scala
+3 −3 sim/firesim-lib/src/main/scala/bridgeutils/BridgeAnnotations.scala
+6 −8 sim/firesim-lib/src/main/scala/bridgeutils/ChannelizedHostPort.scala
+2 −2 sim/firesim-lib/src/main/scala/bridgeutils/FAMEUtils.scala
+2 −2 sim/firesim-lib/src/main/scala/bridgeutils/HostPort.scala
+1 −1 sim/firesim-lib/src/main/scala/bridgeutils/Interfaces.scala
+1 −1 sim/firesim-lib/src/main/scala/bridgeutils/SerializationUtils.scala
+8 −9 sim/firesim-lib/src/main/scala/bridgeutils/SimUtils.scala
+3 −2 sim/firesim-lib/src/main/scala/testutils/PeekPokeHarness.scala
+0 −1 sim/firesim-lib/src/test/scala/TestSuiteCommon.scala
+22 −6 sim/make/scala-lint.mk
+2 −2 sim/make/unittest.mk
+1 −1 sim/midas/src/main/scala/junctions/Nasti2AXI4.scala
+0 −3 sim/midas/src/main/scala/junctions/nasti.scala
+4 −4 sim/midas/src/main/scala/midas/ElaborateChiselSubCircuit.scala
+2 −3 sim/midas/src/main/scala/midas/models/dram/BankConflictModel.scala
+62 −64 sim/midas/src/main/scala/midas/models/dram/FASEDMemoryTimingModel.scala
+3 −3 sim/midas/src/main/scala/midas/models/dram/Util.scala
+1 −1 sim/midas/src/main/scala/midas/passes/SimulationMapping.scala
+3 −3 sim/midas/src/main/scala/midas/widgets/CutBoundaryBridge.scala
+1 −1 sim/midas/src/main/scala/midas/widgets/FuzzingUIntSource.scala
+1 −1 sim/midas/src/main/scala/midas/widgets/PlusArgsBridge.scala
+1 −1 sim/midas/src/main/scala/midas/widgets/TerminationBridge.scala
+5 −5 sim/midas/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+0 −1 sim/midas/src/test/scala/firrtl/testutils/PassTests.scala
+1 −3 sim/midas/src/test/scala/midas/BridgeTopWiringSpec.scala
+0 −1 sim/midas/src/test/scala/midas/CheckCombLogicSpec.scala
+2 −6 sim/midas/src/test/scala/midas/CoerceAsyncToSyncResetSpec.scala
+5 −4 sim/midas/src/test/scala/midas/ElaborationUtils.scala
+2 −2 sim/midas/src/test/scala/midas/FAMEAnnotationSerializationSpec.scala
+4 −6 sim/midas/src/test/scala/midas/FindClockSourcesSpec.scala
+1 −2 sim/midas/src/test/scala/midas/FooTransform.scala
+3 −2 sim/midas/src/test/scala/midas/FpgaDebugSpec.scala
+12 −33 sim/midas/src/test/scala/midas/NoCPartitionSpec.scala
+9 −27 sim/midas/src/test/scala/midas/PartitionSpec.scala
+3 −2 sim/midas/src/test/scala/midas/PerfCounterSpec.scala
+3 −3 sim/midas/src/test/scala/midas/RAMStyleHintSpec.scala
+1 −3 sim/midas/src/test/scala/midas/core/SimUtilsSpec.scala
+3 −4 sim/midas/src/test/scala/midas/passes/AutoILATransformSpec.scala
+0 −2 sim/midas/src/test/scala/midas/passes/WriteXDCFileSpec.scala
+1 −1 sim/midas/src/test/scala/midas/stage/ChecksSpec.scala
+1 −5 sim/midas/src/test/scala/midas/widgets/ChannelizedHostPortIOSpec.scala
+0 −3 sim/midas/src/test/scala/midas/widgets/PlusArgsBridgeSpec.scala
+4 −5 sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala
+2 −2 sim/midas/targetutils/src/main/scala/midas/Utils.scala
+22 −23 sim/midas/targetutils/src/main/scala/midas/annotations.scala
+1 −1 sim/midas/targetutils/src/main/scala/midas/xdc/QSFPPortLocHint.scala
+2 −2 sim/midas/targetutils/src/main/scala/midas/xdc/RAMStyleHint.scala
+4 −5 sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala
+7 −6 sim/src/main/scala/fasedtests/Config.scala
+7 −3 sim/src/main/scala/midasexamples/Config.scala
+3 −1 sim/src/main/scala/midasexamples/CustomConstraints.scala
+4 −3 sim/src/main/scala/midasexamples/GlobalResetConditionTests.scala
+8 −0 sim/src/main/scala/midasexamples/PointerChaser.scala
+10 −22 sim/src/test/scala/fasedtests/FASEDTestSuite.scala
+1 −1 sim/src/test/scala/midasexamples/AssertSuite.scala
+9 −15 sim/src/test/scala/midasexamples/AutoCounterSuite.scala
+4 −4 sim/src/test/scala/midasexamples/ChiselExampleDesigns.scala
+6 −7 sim/src/test/scala/midasexamples/FMRSuite.scala
+2 −6 sim/src/test/scala/midasexamples/MemorySuite.scala
+3 −3 sim/src/test/scala/midasexamples/PlusArgSuite.scala
+11 −12 sim/src/test/scala/midasexamples/PrintfSuite.scala
+1 −5 sim/src/test/scala/midasexamples/TutorialSuite.scala
+7 −8 sim/src/test/scala/unittest/UnitTestSuite.scala
+1 −1 target-design/chipyard

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