Support lazily constructing I/O bundles in the TestHarness

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -16,24 +16,24 @@ import chipyard.iobinders._
 
 class WithArtyDebugResetHarnessBinder extends HarnessBinder({
   case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
-    th.dut_ndreset := port.io // Debug module reset
+    th.dut_ndreset := port.io() // Debug module reset
   }
 })
 
 class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
   case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
-    port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
+    port.io() := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
   }
 })
 
 class WithArtyJTAGHarnessBinder extends HarnessBinder({
   case (th: ArtyFPGATestHarness, port: JTAGPort) => {
     val jtag_wire = Wire(new JTAGIO)
-    jtag_wire.TDO.data := port.io.TDO
+    jtag_wire.TDO.data := port.io().TDO
     jtag_wire.TDO.driven := true.B
-    port.io.TCK := jtag_wire.TCK
-    port.io.TMS := jtag_wire.TMS
-    port.io.TDI := jtag_wire.TDI
+    port.io().TCK := jtag_wire.TCK
+    port.io().TMS := jtag_wire.TMS
+    port.io().TDI := jtag_wire.TDI
 
     val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
 
@@ -64,8 +64,8 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
 class WithArtyUARTHarnessBinder extends HarnessBinder({
   case (th: ArtyFPGATestHarness, port: UARTPort) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
-      IOBUF(th.uart_rxd_out,  port.io.txd)
-      port.io.rxd := IOBUF(th.uart_txd_in)
+      IOBUF(th.uart_rxd_out,  port.io().txd)
+      port.io().rxd := IOBUF(th.uart_txd_in)
     }
   }
 })

fpga/src/main/scala/arty/IOBinders.scala

@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
     val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
     sjtag.reset := io_sjtag_reset
 
-    (Seq(DebugResetPort(io_ndreset), JTAGResetPort(io_sjtag_reset)), Nil)
+    (Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
   }
 })

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -23,12 +23,12 @@ import testchipip._
 class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    ath.io_uart_bb.bundle <> port.io.uart
-    ath.other_leds(1) := port.io.dropped
-    ath.other_leds(9) := port.io.tsi2tl_state(0)
-    ath.other_leds(10) := port.io.tsi2tl_state(1)
-    ath.other_leds(11) := port.io.tsi2tl_state(2)
-    ath.other_leds(12) := port.io.tsi2tl_state(3)
+    ath.io_uart_bb.bundle <> port.io().uart
+    ath.other_leds(1) := port.io().dropped
+    ath.other_leds(9) := port.io().tsi2tl_state(0)
+    ath.other_leds(10) := port.io().tsi2tl_state(1)
+    ath.other_leds(11) := port.io().tsi2tl_state(2)
+    ath.other_leds(12) := port.io().tsi2tl_state(3)
   }
 })
 
@@ -38,6 +38,6 @@ class WithArty100TDDRTL extends HarnessBinder({
     val bundles = artyTh.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> port.io
+    ddrClientBundle <> port.io()
   }
 })

fpga/src/main/scala/nexysvideo/HarnessBinders.scala

@@ -19,12 +19,12 @@ import chipyard.iobinders._
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
-    nexysvideoth.io_uart_bb.bundle <> port.io.uart
-    nexysvideoth.other_leds(1) := port.io.dropped
-    nexysvideoth.other_leds(2) := port.io.tsi2tl_state(0)
-    nexysvideoth.other_leds(3) := port.io.tsi2tl_state(1)
-    nexysvideoth.other_leds(4) := port.io.tsi2tl_state(2)
-    nexysvideoth.other_leds(5) := port.io.tsi2tl_state(3)
+    nexysvideoth.io_uart_bb.bundle <> port.io().uart
+    nexysvideoth.other_leds(1) := port.io().dropped
+    nexysvideoth.other_leds(2) := port.io().tsi2tl_state(0)
+    nexysvideoth.other_leds(3) := port.io().tsi2tl_state(1)
+    nexysvideoth.other_leds(4) := port.io().tsi2tl_state(2)
+    nexysvideoth.other_leds(5) := port.io().tsi2tl_state(3)
   }
 })
 
@@ -34,6 +34,6 @@ class WithNexysVideoDDRTL extends HarnessBinder({
     val bundles = nexysTh.ddrClient.get.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> port.io
+    ddrClientBundle <> port.io()
   }
 })

fpga/src/main/scala/vc707/HarnessBinders.scala

@@ -17,14 +17,14 @@ import chipyard.iobinders._
 /*** UART ***/
 class WithVC707UARTHarnessBinder extends HarnessBinder({
   case (th: VC707FPGATestHarnessImp, port: UARTPort) => {
-    th.vc707Outer.io_uart_bb.bundle <> port.io
+    th.vc707Outer.io_uart_bb.bundle <> port.io()
   }
 })
 
 /*** SPI ***/
 class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
   case (th: VC707FPGATestHarnessImp, port: SPIPort) => {
-    th.vc707Outer.io_spi_bb.bundle <> port.io
+    th.vc707Outer.io_spi_bb.bundle <> port.io()
   }
 })
 
@@ -34,6 +34,6 @@ class WithVC707DDRMemHarnessBinder extends HarnessBinder({
     val bundles = th.vc707Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> port.io
+    ddrClientBundle <> port.io()
   }
 })

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -16,14 +16,14 @@ import chipyard.iobinders._
 /*** UART ***/
 class WithUART extends HarnessBinder({
   case (th: VCU118FPGATestHarnessImp, port: UARTPort) => {
-    th.vcu118Outer.io_uart_bb.bundle <> port.io
+    th.vcu118Outer.io_uart_bb.bundle <> port.io()
   }
 })
 
 /*** SPI ***/
 class WithSPISDCard extends HarnessBinder({
   case (th: VCU118FPGATestHarnessImp, port: SPIPort) => {
-    th.vcu118Outer.io_spi_bb.bundle <> port.io
+    th.vcu118Outer.io_spi_bb.bundle <> port.io()
   }
 })
 
@@ -33,6 +33,6 @@ class WithDDRMem extends HarnessBinder({
     val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> port.io
+    ddrClientBundle <> port.io()
   }
 })

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -19,21 +19,21 @@ import chipyard.iobinders._
 /*** UART ***/
 class WithBringupUART extends HarnessBinder({
   case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
-    th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
+    th.bringupOuter.io_fmc_uart_bb.bundle <> port.io()
   }
 })
 
 /*** I2C ***/
 class WithBringupI2C extends HarnessBinder({
   case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
-    th.bringupOuter.io_i2c_bb.bundle <> port.io
+    th.bringupOuter.io_i2c_bb.bundle <> port.io()
   }
 })
 
 /*** GPIO ***/
 class WithBringupGPIO extends HarnessBinder({
   case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
-    th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
+    th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io()
   }
 })
 
@@ -43,9 +43,9 @@ class WithBringupTSIHost extends HarnessBinder({
     val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
     val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
     tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    tsiDdrClientBundle <> port.io
+    tsiDdrClientBundle <> port.io()
   }
   case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
-    th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
+    th.bringupOuter.io_tsi_serial_bb.bundle <> port.io()
   }
 })

fpga/src/main/scala/vcu118/bringup/IOBinders.scala

@@ -13,7 +13,7 @@ import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
 
-case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
+case class TSIHostWidgetPort(val io: () => TSIHostWidgetIO)
   extends Port[TSIHostWidgetIO]
 
 class WithTSITLIOPassthrough extends OverrideIOBinder({
@@ -25,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
     require(system.tsiSerial.size == 1)
     val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
     io_tsi_serial_pins_temp <> system.tsiSerial.head
-    (Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
+    (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
   }
 })

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -75,7 +75,7 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
         o.reset := reset_wire
       }
 
-      (Seq(ClockPort(clock_io, 100), ResetPort(reset_io)), clockIOCell ++ resetIOCell)
+      (Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
     }
   }
 })
@@ -113,9 +113,9 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
         val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
         b.clock := clock_io
         b.reset := reset_io
-        ClockPort(clock_io, freq)
+        ClockPort(() => clock_io, freq)
       }.toSeq
-      ((clock_ios :+ ResetPort(reset_io)), Nil)
+      ((clock_ios :+ ResetPort(() => reset_io)), Nil)
     }
   }
 })

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -86,8 +86,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
       o.reset := reset_wire
     }
 
-    ports = ports :+ ClockPort(clock_pad, 100.0)
-    ports = ports :+ ResetPort(reset_pad)
+    ports = ports :+ ClockPort(() => clock_pad, 100.0)
+    ports = ports :+ ResetPort(() => reset_pad)
 
     // For a real chip you should replace this ClockSourceAtFreqFromPlusArg
     // with a blackbox of whatever PLL is being integrated
@@ -104,13 +104,13 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     // Custom Boot
     //=========================
     val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
-    ports = ports :+ CustomBootPort(custom_boot_pad)
+    ports = ports :+ CustomBootPort(() => custom_boot_pad)
 
     //=========================
     // Serialized TileLink
     //=========================
     val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
-    ports = ports :+ SerialTLPort(serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)
+    ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)
 
     //=========================
     // JTAG/Debug
@@ -149,7 +149,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
       IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
     }.get
 
-    ports = ports :+ JTAGPort(jtag_pad)
+    ports = ports :+ JTAGPort(() => jtag_pad)
 
     //==========================
     // UART
@@ -159,7 +159,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     val where = PBUS // TODO fix
     val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
     val freqMHz = bus.dtsFrequency.get / 1000000
-    ports = ports :+ UARTPort(uart_pad, 0, freqMHz.toInt)
+    ports = ports :+ UARTPort(() => uart_pad, 0, freqMHz.toInt)
 
     //==========================
     // External interrupts (tie off)