Merge pull request #1630 from ucb-bar/tcip-bump

Bump testchipip to support multi-serial-tl

fpga/src/main/scala/arty/Configs.scala

@@ -27,6 +27,8 @@ class WithArtyTweaks extends Config(
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.config.WithDTSTimebase(32000) ++
   new chipyard.config.WithSystemBusFrequency(32) ++
+  new chipyard.config.WithFrontBusFrequency(32) ++
+  new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
   new testchipip.WithNoSerialTL
 )

fpga/src/main/scala/nexysvideo/Configs.scala

@@ -33,6 +33,7 @@ class WithNexysVideoTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(50.0) ++
   new chipyard.config.WithSystemBusFrequency(50.0) ++
   new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+  new chipyard.config.WithControlBusFrequency(50.0) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag
@@ -69,4 +70,4 @@ class TinyRocketNexysVideoConfig extends Config(
   new WithTinyNexysVideoTweaks ++
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.TinyRocketConfig)
-  // DOC include end: WithTinyNexysVideoTweaks and Rocket
+  // DOC include end: WithTinyNexysVideoTweaks and Rocket

fpga/src/main/scala/vc707/Configs.scala

@@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => {
     p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
   }
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
-  case SerialTLKey => None // remove serialized tl port
+  case SerialTLKey => Nil // remove serialized tl port
 })
 
 class WithVC707Tweaks extends Config (
@@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config (
   new chipyard.config.WithMemoryBusFrequency(50.0) ++
   new chipyard.config.WithSystemBusFrequency(50.0) ++
   new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+  new chipyard.config.WithControlBusFrequency(50.0) ++
+  new chipyard.config.WithFrontBusFrequency(50.0) ++
 
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new WithFPGAFrequency(50) ++ // default 50MHz freq
@@ -74,8 +76,11 @@ class BoomVC707Config extends Config (
 )
 
 class WithFPGAFrequency(fMHz: Double) extends Config (
-  new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
-  new chipyard.config.WithMemoryBusFrequency(fMHz)
+  new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
+  new chipyard.config.WithMemoryBusFrequency(fMHz) ++
+  new chipyard.config.WithSystemBusFrequency(fMHz) ++
+  new chipyard.config.WithControlBusFrequency(fMHz) ++
+  new chipyard.config.WithFrontBusFrequency(fMHz)
 )
 
 class WithFPGAFreq25MHz extends WithFPGAFrequency(25)

fpga/src/main/scala/vcu118/Configs.scala

@@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => {
     p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
   }
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
-  case SerialTLKey => None // remove serialized tl port
+  case SerialTLKey => Nil // remove serialized tl port
 })
 
 // DOC include start: AbstractVCU118 and Rocket
@@ -46,6 +46,7 @@ class WithVCU118Tweaks extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithMemoryBusFrequency(100) ++
   new chipyard.config.WithSystemBusFrequency(100) ++
+  new chipyard.config.WithControlBusFrequency(100) ++
   new chipyard.config.WithPeripheryBusFrequency(100) ++
   new WithFPGAFrequency(100) ++ // default 100MHz freq
   // harness binders
@@ -76,7 +77,9 @@ class BoomVCU118Config extends Config(
 class WithFPGAFrequency(fMHz: Double) extends Config(
   new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
   new chipyard.config.WithSystemBusFrequency(fMHz) ++
-  new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
+  new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
+  new chipyard.config.WithControlBusFrequency(fMHz) ++
+  new chipyard.config.WithFrontBusFrequency(fMHz) ++
   new chipyard.config.WithMemoryBusFrequency(fMHz)
 )
 

generators/chipyard/src/main/scala/Subsystem.scala

@@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
   if (this match {
-    case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
+    case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true
     case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
     case _ => false
   }) {

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -53,15 +53,20 @@ class AbstractConfig extends Config(
 
   // By default, punch out IOs to the Harness
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
+  new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
+  new chipyard.config.WithSystemBusFrequency(500.0) ++              // Default 500 MHz sbus
+  new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
+  new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
   new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address
   new testchipip.WithBootAddrReg ++                                 // add a boot-addr-reg for configurable boot address
-  new testchipip.WithSerialTLClientIdBits(4) ++                     // support up to 1 << 4 simultaneous requests from serialTL port
-  new testchipip.WithSerialTLWidth(32) ++                           // fatten the serialTL interface to improve testing performance
-  new testchipip.WithDefaultSerialTL ++                             // use serialized tilelink port to external serialadapter/harnessRAM
+  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(        // add a serial-tilelink interface
+    client = Some(testchipip.SerialTLClientParams(idBits = 4)),     // serial-tilelink interface will master the FBUS, and support 4 idBits
+    width = 32                                                      // serial-tilelink interface with 32 lanes
+  ))) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -23,8 +23,8 @@ class ChipLikeRocketConfig extends Config(
   // Set up I/O
   //==================================
   new testchipip.WithSerialTLWidth(4) ++                                                // 4bit wide Serialized TL interface to minimize IO
-  new testchipip.WithSerialTLBackingMemory ++                                           // Configure the off-chip memory accessible over serial-tl as backing memory
-  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++                  // 4GB max external memory
+  new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++                              // Configure the off-chip memory accessible over serial-tl as backing memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 
   //==================================
@@ -89,6 +89,9 @@ class ChipBringupHostConfig extends Config(
   new chipyard.config.WithFrontBusFrequency(75.0) ++     // run all buses of this system at 75 MHz
   new chipyard.config.WithMemoryBusFrequency(75.0) ++
   new chipyard.config.WithPeripheryBusFrequency(75.0) ++
+  new chipyard.config.WithSystemBusFrequency(75.0) ++
+  new chipyard.config.WithControlBusFrequency(75.0) ++
+  new chipyard.config.WithOffchipBusFrequency(75.0) ++
 
   // Base is the no-cores config
   new chipyard.NoCoresConfig)

generators/chipyard/src/main/scala/config/NoCConfigs.scala

@@ -46,7 +46,7 @@ import scala.collection.immutable.ListMap
  *   | SI:Core 2    | SO:system[0] | SO:system[1] | SI:Core 3    |
  *   |(0)___________|(1)___________|(2)___________|(3)___________|
  *   | FBus         | Core 0       | Core 1       | Pbus         |
- *   | SI:serial-tl | SI:Core 0    | SI:Core 1    | SO:pbus      |
+ *   | SI:serial_tl | SI:Core 0    | SI:Core 1    | SO:pbus      |
  *   |______________|______________|______________|______________|
  *
  *   |(0)___________|(1)___________|(2)___________|(3)___________|
@@ -66,7 +66,7 @@ class MultiNoCConfig extends Config(
   new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
-        "serial-tl" -> 0),
+        "serial_tl" -> 0),
       outNodeMapping = ListMap(
         "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
         "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
@@ -82,7 +82,7 @@ class MultiNoCConfig extends Config(
         "L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
       outNodeMapping = ListMap(
         "system[0]" -> 0, "system[1]" -> 3,  "system[2]" -> 4 , "system[3]" -> 7,
-        "serdesser" -> 0)),
+        "serial_tl_0" -> 0)),
     NoCParams(
       topology        = TerminalRouter(BidirectionalTorus1D(8)),
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
@@ -93,7 +93,7 @@ class MultiNoCConfig extends Config(
       inNodeMapping = ListMap(
         "Core 0" -> 1, "Core 1" -> 2,  "Core 2" -> 4 , "Core 3" -> 7,
         "Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14,
-        "serial-tl" -> 0),
+        "serial_tl" -> 0),
       outNodeMapping = ListMap(
         "system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10,
         "pbus" -> 3)),
@@ -134,7 +134,7 @@ class MultiNoCConfig extends Config(
  * Core 6 | SI  | Core 6     |   16
  * Core 7 | SI  | Core 7     |   18
  * Core 8 | SI  | Core 8     |   19
- * fbus   | SI  | serial-tl  |    9
+ * fbus   | SI  | serial_tl  |    9
  * pbus   | SO  | pbus       |    4
  * L2 0   | SO  | system[0]  |    0
  * L2 1   | SO  | system[1]  |    2
@@ -146,7 +146,7 @@ class MultiNoCConfig extends Config(
  * L2 3   | MI  | Cache[3]   |    6
  * DRAM 0 | MO  | system[0]  |    3
  * DRAM 1 | MO  | system[1]  |    5
- * extram | MO  | serdesser  |    9
+ * extram | MO  | serial_tl_0  |    9
  */
 // DOC include start: SharedNoCConfig
 class SharedNoCConfig extends Config(
@@ -169,12 +169,12 @@ class SharedNoCConfig extends Config(
         "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
       outNodeMapping = ListMap(
         "system[0]" -> 3, "system[1]" -> 5,
-        "serdesser" -> 9))
+        "serial_tl_0" -> 9))
   )) ++
   new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
-        "serial-tl" -> 9, "Core 0" -> 2,
+        "serial_tl" -> 9, "Core 0" -> 2,
         "Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14,
         "Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19),
       outNodeMapping = ListMap(
@@ -201,7 +201,7 @@ class SbusRingNoCConfig extends Config(
         "Core 5" -> 5,
         "Core 6" -> 6,
         "Core 7" -> 7,
-        "serial-tl" -> 8),
+        "serial_tl" -> 8),
       outNodeMapping = ListMap(
         "system[0]" -> 9,
         "system[1]" -> 10,

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -52,6 +52,9 @@ class MMIORocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(
+  new chipyard.config.WithOffchipBusFrequency(500) ++
+  new testchipip.WithOffchipBusClient(MBUS) ++
+  new testchipip.WithOffchipBus ++
   new testchipip.WithSerialTLMem(isMainMemory=true) ++      // set lbwif memory base to DRAM_BASE, use as main memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove AXI4 backing memory
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -69,7 +69,6 @@ class MulticlockRocketConfig extends Config(
   new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
   new chipyard.config.AbstractConfig)
 
 class CustomIOChipTopRocketConfig extends Config(

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -15,6 +15,8 @@ import chipyard._
 import chipyard.clocking._
 import testchipip.{OffchipBusKey}
 
+import testchipip.{OffchipBusKey}
+
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
 // the diplomacy graph upwards into the ChipTop, where we connect it to

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -1,7 +1,7 @@
 package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy.{DTSTimebase}
 import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
@@ -10,6 +10,10 @@ class WithBroadcastManager extends Config((site, here, up) => {
   case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
 })
 
+class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {
+  case BroadcastKey => params
+})
+
 class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
 })
@@ -26,4 +30,4 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
 // Adds buffers on the exterior of the inclusive LLC, to improve PD
 class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
   case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
-})                                                                                                                                                                                                                 
+})

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -109,8 +109,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     //=========================
     // Serialized TileLink
     //=========================
-    val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
-    ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)
+    val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey))
+    ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey)(0), system.serdessers(0), 0)
 
     //=========================
     // JTAG/Debug

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -39,8 +39,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
   dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
 
   // Serialized TL
-  val sVal = p(SerialTLKey).get
-  val serialTLManagerParams = sVal.serialTLManagerParams.get
+  val sVal = p(SerialTLKey)(0)
+  val serialTLManagerParams = sVal.manager.get
   require(serialTLManagerParams.isMemoryDevice)
 
   withClockAndReset(clock, reset) {
@@ -49,10 +49,11 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
       dut.serial_tl_pad.clock := clock
     }
     val harnessRAM = TSIHarness.connectRAM(
-      lazyDut.system.serdesser.get,
+      p(SerialTLKey)(0),
+      lazyDut.system.serdessers(0),
       serial_bits,
       reset)
-    io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
+    io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset)
 
   }
 

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -215,13 +215,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
     if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
       port.io.clock := th.harnessBinderClock
     }
-    val ram = LazyModule(new SerialRAM(port.serdesser)(port.serdesser.p))
+    val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
     Module(ram.module)
     ram.module.io.ser <> port.io.bits
     val tsi = Module(new SimTSI)
     tsi.io.clock := th.harnessBinderClock
     tsi.io.reset := th.harnessBinderReset
-    tsi.io.tsi <> ram.module.io.tsi
+    tsi.io.tsi <> ram.module.io.tsi.get
     val exit = tsi.io.exit
     val success = exit === 1.U
     val error = exit >= 2.U

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -334,22 +334,22 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
 
 class WithSerialTLIOCells extends OverrideIOBinder({
   (system: CanHavePeripheryTLSerial) => {
-    val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
+    val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
       val sys = system.asInstanceOf[BaseSubsystem]
-      val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true)
-      (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells)
+      val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
+      (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
     }).unzip
     (ports.toSeq, cells.flatten.toSeq)
   }
 })
 
 class WithSerialTLPunchthrough extends OverrideIOBinder({
   (system: CanHavePeripheryTLSerial) => {
-    val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
+    val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
       val sys = system.asInstanceOf[BaseSubsystem]
       val port = IO(chiselTypeOf(s.getWrappedValue))
       port <> s.getWrappedValue
-      (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil)
+      (SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
     }).unzip
     (ports.toSeq, cells.flatten.toSeq)
   }

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -69,7 +69,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
   case (th: FireSim, port: SerialTLPort) => {
     val bits = port.io.bits
     port.io.clock := th.harnessBinderClock
-    val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty))
+    val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
     Module(ram.module)
     ram.module.io.ser <> port.io.bits
 
@@ -78,7 +78,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
     // If FASED bridge is attached, loadmem widget is present
     val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
     val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
-    TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
+    TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
   }
 })