Support not instantiating the TileClockGater/ResetSetter PRCI control…

…lers (#1459)
ucb-bar · May 5, 2023 · b8ccb7d · b8ccb7d
1 parent b05f36d
commit b8ccb7d
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Showing 2 changed files with 12 additions and 10 deletions.
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -20,7 +20,8 @@ import chipyard.{DefaultClockFrequencyKey}
 case class ChipyardPRCIControlParams(
   slaveWhere: TLBusWrapperLocation = CBUS,
   baseAddress: BigInt = 0x100000,
-  enableTileClockGating: Boolean = true
+  enableTileClockGating: Boolean = true,
+  enableTileResetSetting: Boolean = true
 )
 
 
@@ -72,12 +73,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
   val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
   val clockGroupCombiner = ClockGroupCombiner()
   val resetSynchronizer  = ClockGroupResetSynchronizer()
-  val tileClockGater     = prci_ctrl_domain {
-    TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating)
-  }
-  val tileResetSetter    = prci_ctrl_domain {
+  val tileClockGater     = if (prciParams.enableTileClockGating) { prci_ctrl_domain {
+    TileClockGater(prciParams.baseAddress + 0x00000, tlbus)
+  } } else { ClockGroupEphemeralNode() }
+  val tileResetSetter    = if (prciParams.enableTileResetSetting) { prci_ctrl_domain {
     TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
-  }
+  } } else { ClockGroupEphemeralNode() }
+
   (aggregator
     := frequencySpecifier
     := clockGroupCombiner

diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -19,7 +19,7 @@ import freechips.rocketchip.subsystem._
   * flag will generate the registers, preserving the same memory map and behavior, but will not
   * generate any gaters
   */
-class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule
+class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule
 {
   val device = new SimpleDevice(s"clock-gater", Nil)
   val clockNode = ClockGroupIdentityNode()
@@ -31,7 +31,7 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit
     val regs = (0 until nSinks).map({i =>
       val sinkName = sinks(i)._1
       val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) }
-      if (sinkName.contains("tile") && enable) {
+      if (sinkName.contains("tile")) {
         println(s"${(address+i*4).toString(16)}: Tile $sinkName clock gate")
         sinks(i)._2.clock := ClockGate(sources(i).clock,  reg.io.q.asBool)
         sinks(i)._2.reset := sources(i).reset
@@ -47,8 +47,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit
 }
 
 object TileClockGater {
-  def apply(address: BigInt, tlbus: TLBusWrapper, enable: Boolean)(implicit p: Parameters, v: ValName) = {
-    val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes, enable))
+  def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
+    val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
     tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() }
     gater.clockNode
   }