[ci skip] sketch

ucb-bar · Apr 20, 2024 · e1e6fe2 · e1e6fe2
1 parent 6100544
commit e1e6fe2
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Showing 3 changed files with 61 additions and 10 deletions.
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -9,6 +9,7 @@ import freechips.rocketchip.subsystem.{InCluster}
 // --------------
 
 class RocketConfig extends Config(
+  new chipyard.config.ResolveTileBootFrequencies ++              // assign the tile boot frequency in the DTS
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
@@ -22,6 +23,7 @@ class TinyRocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class QuadRocketConfig extends Config(
+  new chipyard.config.ResolveTileBootFrequencies() ++
   new freechips.rocketchip.subsystem.WithNBigCores(4) ++    // quad-core (4 RocketTiles)
   new chipyard.config.AbstractConfig)
 

diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -29,13 +29,16 @@ class WithNoSubsystemClockIO extends Config((site, here, up) => {
   * @param fMHz Frequency in MHz of the tile or all tiles
   * @param hartId Optional hartid to assign the frequency to (if unspecified default to all harts)
   */
-class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({
-    hartId match {
-      case Some(id) => s"tile_$id"
-      case None => "tile"
-    }
-  },
-  fMHz)
+class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends
+  new WithDTSTileBootFrequency(fMHz, hartId) ++ // also set the DTS freq
+  new ClockNameContainsAssignment({
+      hartId match {
+        case Some(id) => s"tile_$id"
+        case None => "tile"
+      }
+    },
+    fMHz)
+)
 
 class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {
   case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
@@ -98,9 +101,12 @@ class WithPeripheryBusFrequency(freqMHz: Double) extends Config(
 class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
   case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
-class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
-})
+class WithSystemBusFrequency(freqMHz: Double) extends Config(
+  new WithDTSTileBootFrequency(freqMHz) ++
+  new Config((site, here, up) => {
+    case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  })
+)
 class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
   case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })

diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -131,3 +131,46 @@ class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams]
 class WithSV48IfPossible extends Config((site, here, up) => {
   case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
 })
+
+// Set of all hartIds directly modified by WithDTSTileBootFrequency
+case object DTSTileBootFrequencySetKey extends Field[Set[Int]](Set.empty[Int])
+
+/**
+  * Assigns the bootFreqHz parameter of a core (used to set the DTS `cpu-frequency` parameter).
+  * If hartIds are re-assigned this config. frag. will not work.
+  *
+  * @param fMHz Frequency in MHz of the tile or all tiles
+  * @param hartId Optional hartid to assign the frequency to (if unspecified either default to all harts or none of them based on 'selective')
+  * @param setUnset If 'hardId' = None && 'setUnset' then only set the harts which haven't been set (otherwise do nothing)
+  */
+class WithDTSTileBootFrequency(fMHz: Double, hartId: Option[Int] = None, setUnset: Boolean = true) extends Config((site, here, up) => {
+  case DTSTileBootFrequencySetKey => {
+    hartId match {
+      case Some(id) => up(DTSTileBootFrequencySetKey) + hartId
+      case None => up(DTSTileBootFrequencySetKey)
+    }
+  }
+  case TilesLocated(InSubsystem) => {
+    def setTileParamsFreq() = ???
+    up(TilesLocated(InSubsystem), site) map {
+      case tp => hartId match {
+        case Some(id) => {
+          if (tp.hartId == id) {
+            tp.copy(core = tp.core.copy(bootFreqHz = fMHz * 1e3))
+          } else {
+            tp
+          }
+        }
+        case None => {
+          if (setUnset) {
+            if (!up(DTSTileBootFrequencySetKey).contains(tp.hartId))
+              tp.copy(core = tp.core.copy(bootFreqHz = fMHz * 1e3))
+              up()
+          } else {
+            tp
+          }
+        }
+      }
+    }
+  }
+})