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Use SV48 when possible
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abejgonzalez committed Apr 12, 2024
1 parent 766ea73 commit f5a4a51
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Showing 2 changed files with 9 additions and 1 deletion.
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,7 @@ class AbstractConfig extends Config(

// Bus/interconnect settings
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */


// ================================================
Expand All @@ -134,7 +135,7 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("tile"))) ++

new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,8 @@ import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
import freechips.rocketchip.rocket.{PgLevels}
import freechips.rocketchip.tile.{XLen}

// Replaces the L2 with a broadcast manager for maintaining coherence
class WithBroadcastManager extends Config((site, here, up) => {
Expand Down Expand Up @@ -31,3 +33,8 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
})

// Uses SV48 if possible, otherwise default to the Rocket core default
class WithSV48IfPossible extends Config((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
})

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