Prototype build for VCU118 fails complaining about discrepancy in ClockParameters in v1.10.0

[faridsamandi]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.10.0
Hash: b7644b2

OS Setup

Linux 5.4.0-153-generic x86_64 GNU/Linux
Ubuntu 20.04.6 LTS

Other Setup

Followed the documentation:
./build-setup.sh riscv-tools
source ./env.sh
cd fpga
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bitstream

Current Behavior

I use this configuration:

Upon running make I get error. Here is the last part of output:

<stdin>:128.26-133.5: Warning (simple_bus_reg): /soc/subsystem_l2_clock: missing or empty reg/ranges property                                                                                                                                 
<stdin>:134.28-139.5: Warning (simple_bus_reg): /soc/subsystem_mbus_clock: missing or empty reg/ranges property                                                                                                                               
<stdin>:140.28-145.5: Warning (simple_bus_reg): /soc/subsystem_pbus_clock: missing or empty reg/ranges property                                                                                                                               
<stdin>:146.28-151.5: Warning (simple_bus_reg): /soc/subsystem_sbus_clock: missing or empty reg/ranges property
<stdin>:42.29-46.6: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
<stdin>:88.36-97.5: Warning (interrupt_provider): /soc/interrupt-controller@c000000: Missing #address-cells in interrupt provider
Clock subsystem_sbus_0: using diplomatically specified frequency of 100.0.
Clock subsystem_sbus_1: using diplomatically specified frequency of 100.0.
Clock subsystem_pbus_0: using diplomatically specified frequency of 50.0.
Clock subsystem_mbus_0: using diplomatically specified frequency of 50.0.
Exception in thread "main" java.lang.IllegalArgumentException: requirement failed: Clock group uncore has non-homogeneous requested ClockParameters List(ClockParameters(100.0,50.0), ClockParameters(100.0,50.0), ClockParameters(50.0,50.0), ClockParameters(50.0,50.0))
        at ... ()
        at chipyard.clocking.ClockGroupCombiner.$anonfun$sinkFn$3(ClockGroupCombiner.scala:53)
        at scala.collection.immutable.ArraySeq.foldLeft(ArraySeq.scala:222)
        at chipyard.clocking.ClockGroupCombiner.$anonfun$sinkFn$1(ClockGroupCombiner.scala:46)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at freechips.rocketchip.diplomacy.MixedAdapterNode.mapParamsU(Nodes.scala:1488)
        at freechips.rocketchip.diplomacy.MixedNode.liftedTree3$1(Nodes.scala:1177)
        at freechips.rocketchip.diplomacy.MixedNode.uiParams$lzycompute(Nodes.scala:1174)
        at freechips.rocketchip.diplomacy.MixedNode.uiParams(Nodes.scala:1173)
        at freechips.rocketchip.diplomacy.MixedNode.$anonfun$uoParams$1(Nodes.scala:1172)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at freechips.rocketchip.diplomacy.MixedNode.uoParams$lzycompute(Nodes.scala:1172)
        at freechips.rocketchip.diplomacy.MixedNode.uoParams(Nodes.scala:1172)
        at freechips.rocketchip.diplomacy.MixedNode.liftedTree3$1(Nodes.scala:1177)
        at freechips.rocketchip.diplomacy.MixedNode.uiParams$lzycompute(Nodes.scala:1174)
        at freechips.rocketchip.diplomacy.MixedNode.uiParams(Nodes.scala:1173)
        at freechips.rocketchip.diplomacy.MixedNode.edgesIn$lzycompute(Nodes.scala:1196)
        at freechips.rocketchip.diplomacy.MixedNode.edgesIn(Nodes.scala:1196)
        at freechips.rocketchip.diplomacy.MixedNode.$anonfun$bundleIn$2(Nodes.scala:1215)
        at chisel3.internal.prefix$.apply(prefix.scala:48)
        at freechips.rocketchip.diplomacy.MixedNode.$anonfun$bundleIn$1(Nodes.scala:1215)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.diplomacy.MixedNode.bundleIn$lzycompute(Nodes.scala:1215)
        at freechips.rocketchip.diplomacy.MixedNode.bundleIn(Nodes.scala:1215)
        at freechips.rocketchip.diplomacy.MixedNode.in(Nodes.scala:1266)
        at freechips.rocketchip.diplomacy.MixedNode.instantiate(Nodes.scala:1277)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$16(LazyModule.scala:341)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:341)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:305)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:401)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$2(LazyModule.scala:414)
        at chisel3.withClockAndReset$.apply(MultiClock.scala:26)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$1(LazyModule.scala:414)
        at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.<init>(LazyModule.scala:413)
        at freechips.rocketchip.prci.ClockGroupResetSynchronizer$Impl.<init>(ResetSynchronizer.scala:33)
        at freechips.rocketchip.prci.ClockGroupResetSynchronizer.$anonfun$module$2(ResetSynchronizer.scala:32)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.prci.ClockGroupResetSynchronizer.module$lzycompute(ResetSynchronizer.scala:32)
        at freechips.rocketchip.prci.ClockGroupResetSynchronizer.module(ResetSynchronizer.scala:32)
        at freechips.rocketchip.prci.ClockGroupResetSynchronizer.module(ResetSynchronizer.scala:30)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:334)
        at chisel3.Module$.do_apply(Module.scala:53)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:334)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:334)
        at scala.Option.getOrElse(Option.scala:201)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:332)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:308)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:305)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:401)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$2(LazyModule.scala:414)
        at chisel3.withClockAndReset$.apply(MultiClock.scala:26)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$1(LazyModule.scala:414)
        at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.<init>(LazyModule.scala:413)
        at freechips.rocketchip.prci.Domain$Impl.<init>(ClockDomain.scala:11)
        at freechips.rocketchip.prci.Domain.$anonfun$module$1(ClockDomain.scala:10)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.prci.Domain.module$lzycompute(ClockDomain.scala:10)
        at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:10)
        at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:7)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:334)
        at chisel3.Module$.do_apply(Module.scala:53)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:334)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:334)
        at scala.Option.getOrElse(Option.scala:201)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:332)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:308)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:305)
        at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:392)
        at freechips.rocketchip.diplomacy.LazyModuleImp.$anonfun$x$22$1(LazyModule.scala:394)
        at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48)
        at freechips.rocketchip.diplomacy.LazyModuleImp.<init>(LazyModule.scala:394)
        at freechips.rocketchip.subsystem.BareSubsystemModuleImp.<init>(BaseSubsystem.scala:29)
        at freechips.rocketchip.subsystem.BaseSubsystemModuleImp.<init>(BaseSubsystem.scala:122)
        at chipyard.ChipyardSubsystemModuleImp.<init>(Subsystem.scala:124)
        at chipyard.ChipyardSystemModule.<init>(System.scala:48)
        at chipyard.DigitalTopModule.<init>(DigitalTop.scala:41)
        at chipyard.DigitalTop.$anonfun$module$1(DigitalTop.scala:38)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at chipyard.DigitalTop.module$lzycompute(DigitalTop.scala:38)
        at chipyard.DigitalTop.module(DigitalTop.scala:38)
        at chipyard.DigitalTop.module(DigitalTop.scala:15)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:334)
        at chisel3.Module$.do_apply(Module.scala:53)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:334)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:334)
        at scala.Option.getOrElse(Option.scala:201)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:332)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:308)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:305)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:401)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$2(LazyModule.scala:414)
        at chisel3.withClockAndReset$.apply(MultiClock.scala:26)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$1(LazyModule.scala:414)
        at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.<init>(LazyModule.scala:413)
        at chipyard.ChipTop$$anon$1.<init>(ChipTop.scala:34)
        at chipyard.ChipTop.$anonfun$module$1(ChipTop.scala:34)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at chipyard.ChipTop.module$lzycompute(ChipTop.scala:34)
        at chipyard.ChipTop.module(ChipTop.scala:34)
        at chipyard.harness.HasHarnessInstantiators.$anonfun$instantiateChipTops$5(HasHarnessInstantiators.scala:82)
        at chisel3.Module$.do_apply(Module.scala:53)
        at chipyard.harness.HasHarnessInstantiators.$anonfun$instantiateChipTops$4(HasHarnessInstantiators.scala:82)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at chipyard.harness.HasHarnessInstantiators.$anonfun$instantiateChipTops$3(HasHarnessInstantiators.scala:82)
        at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
        at chipyard.harness.HasHarnessInstantiators.instantiateChipTops(HasHarnessInstantiators.scala:82)
        at chipyard.harness.HasHarnessInstantiators.instantiateChipTops$(HasHarnessInstantiators.scala:75)
        at chipyard.fpga.vcu118.VCU118FPGATestHarnessImp.instantiateChipTops(TestHarness.scala:93)
        at chipyard.fpga.vcu118.VCU118FPGATestHarnessImp.<init>(TestHarness.scala:127)
        at chipyard.fpga.vcu118.VCU118FPGATestHarness.module$lzycompute(TestHarness.scala:90)
        at chipyard.fpga.vcu118.VCU118FPGATestHarness.module(TestHarness.scala:90)
        at chipyard.fpga.vcu118.VCU118FPGATestHarness.module(TestHarness.scala:24)
        at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:38)
        at ... ()
        at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
make: *** [/home/farid/chipyard/common.mk:132: /home/farid/chipyard/fpga/generated-src/chipyard.fpga.vcu118.VCU118FPGATestHarness.BoomVCU118Config/chipyard.fpga.vcu118.VCU118FPGATestHarness.BoomVCU118Config.fir] Error 1

Expected Behavior

The build finishing successfully.

Other Information

I don't face this issue with previous versions, like 1.9.0.