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Small QOL fixes for Xcelium #1485

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May 26, 2023
Merged

Small QOL fixes for Xcelium #1485

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45 changes: 21 additions & 24 deletions sims/xcelium/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug


#########################################################################################
# xcelium simulator rules
#########################################################################################
Expand All @@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)

$(sim_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
echo "run" >> $(sim_run_tcl)
echo "exit" >> $(sim_run_tcl)
echo "$$CAD_INFO_HEADER" > $@
echo "run" >> $@
echo "exit" >> $@

# The system libstdc++ may not link correctly with some of our dynamic libs, so
# force loading the conda one (if present) with LD_PRELOAD
$(sim): $(sim_workdir) $(sim_run_tcl)
echo "#!/usr/bin/env bash" > $(sim)
echo "$$CAD_INFO_HEADER" >> $(sim)
cat arg-reshuffle >> $(sim)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
chmod +x $(sim)
echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@

$(sim_debug_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
echo "run" >> $(sim_debug_run_tcl)
echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
echo "exit" >> $(sim_debug_run_tcl)

echo "$$CAD_INFO_HEADER" > $@
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
echo "set probe_packed_limit 64k" >> $@
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
echo "run" >> $@
echo "database -close default_vcd_dump" >> $@
echo "exit" >> $@

$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
echo "#!/usr/bin/env bash" > $(sim_debug)
echo "$$CAD_INFO_HEADER" >> $(sim_debug)
cat arg-reshuffle >> $(sim_debug)
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
chmod +x $(sim_debug)

echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@

#########################################################################################
# create vcd rules
Expand Down