Add UART device/JTAG to Arty100T default design

[jerryz123]

The UART and JTAG are mapped to PMOD JD pins.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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[T-K-233]

Vivado gives the following error on pins uart_tsi_tsi2tl_state[3:0] and uart_tsi_dropped when generating bitstream:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 79 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_tsi_tsi2tl_state[3:0], and uart_tsi_dropped.
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 5 out of 79 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: uart_tsi_tsi2tl_state[3:0], and uart_tsi_dropped.

[jerryz123]

^ Does that actually break the build?

[T-K-233]

^ Does that actually break the build?

Yes, vivado gives an error and fails to generate bitstream

[michael-etzkorn]

Vivado does not allow floating IO in the top level of the design by default, so the TSI pins would need to be removed or tied off by default.

They could be tied to unused PMOD pins and set to pulldown. I'd have to pull up the ARTY FPGA pin layout and the generated xdc to find the remaining pins.

# pin contraint here

# iostandard contraint
set_property IOSTANDARD LVCMOS33 [get_ports {uart_tsi_tsi2tl_state[3:0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_tsi_dropped}]

# pulldown
set_property PULLDOWN true [get_ports {uart_tsi_tsi2tl_state[0]}]
set_property PULLDOWN true [get_ports {uart_tsi_tsi2tl_state[1]}]
set_property PULLDOWN true [get_ports {uart_tsi_tsi2tl_state[2]}]
set_property PULLDOWN true [get_ports {uart_tsi_tsi2tl_state[3]}]

set_property PULLDOWN true [get_ports {uart_tsi_dropped}]

If 0 or 1 won't effect the config, the PULLDOWN isn't necessary.

[michael-etzkorn]

From what I can tell, previously, they weren't punched out into the very top harness. If any undefined pins are unconstrained on the top level, it's normal for vivado to throw this error. I can investigate a bit tomorrow if T-K does not have time. Jerry Zhao ***@***.***> 于 2023年12月23日周六 上午10:30写道：

…

***@***.**** commented on this pull request. ------------------------------ In fpga/src/main/scala/arty100t/HarnessBinders.scala <#1712 (comment)>: > @@ -25,7 +25,17 @@ import testchipip._ class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] - ath.io_uart_bb.bundle <> port.io.uart + val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi") + harnessIO <> port.io + val packagePinsWithPackageIOs = Seq( + ("A9" , IOPin(harnessIO.uart.rxd)), + ("D10", IOPin(harnessIO.uart.txd))) What is surprising to me is that this PR does not touch those pins. And I have built bitstreams with those pins working in the past. This needs some investigation — Reply to this email directly, view it on GitHub <#1712 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AVF2DI6DUBVNRMMTIE4G3TTYK4BMHAVCNFSM6AAAAABA5DWFG6VHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMYTOOJVGQ2TGNRTHE> . You are receiving this because you commented.Message ID: ***@***.***>

[jerryz123]

@T-K-233 Try now

[T-K-233]

Working now

[jerryz123]

@T-K-233 thanks!

[jerryz123]

@T-K-233 the comment in your commit is inaccurate. That line adds a separate memory, it does not affect the L1 caches at all.

[T-K-233]

Oh sorry... copilot failed me
This is different from the new freechips.rocketchip.subsystem.WithScratchpadsOnly config.

Fixed now.