Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Nexys video fpga bringup config #1942

Merged
merged 2 commits into from
Aug 6, 2024
Merged

Nexys video fpga bringup config #1942

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
3fb47c3
nexysvideo fpga bringup config
SeahK Aug 2, 2024
e84dbd2
make it compatible with latest chipyard
SeahK Aug 2, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
21 changes: 14 additions & 7 deletions fpga/src/main/scala/nexysvideo/Configs.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,18 +22,19 @@ class WithNoDesignKey extends Config((site, here, up) => {
})

// DOC include start: WithNexysVideoTweaks and Rocket
class WithNexysVideoTweaks extends Config(
class WithNexysVideoTweaks(freqMHz: Double = 50) extends Config(
new WithNexysVideoUARTTSI ++
new WithNexysVideoDDRTL ++
new WithNoDesignKey ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
new chipyard.config.WithFrontBusFrequency(freqMHz) ++
new chipyard.config.WithSystemBusFrequency(freqMHz) ++
new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
new chipyard.config.WithControlBusFrequency(freqMHz) ++
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
Expand Down Expand Up @@ -72,3 +73,9 @@ class TinyRocketNexysVideoConfig extends Config(
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.TinyRocketConfig)
// DOC include end: WithTinyNexysVideoTweaks and Rocket

class BringupNexysVideoConfig extends Config(
new WithNexysVideoSerialTLToGPIO ++
new WithNexysVideoTweaks(freqMHz = 75) ++
new chipyard.ChipBringupHostConfig)

64 changes: 63 additions & 1 deletion fpga/src/main/scala/nexysvideo/HarnessBinders.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,17 +3,27 @@ package chipyard.fpga.nexysvideo

import chisel3._

import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}

import sifive.blocks.devices.uart.{UARTParams}
import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}

//import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._

import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import testchipip.serdes._

class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
Expand All @@ -36,3 +46,55 @@ class WithNexysVideoDDRTL extends HarnessBinder({
ddrClientBundle <> port.io
}
})

// Uses PMOD JA/JB
class WithNexysVideoSerialTLToGPIO extends HarnessBinder({
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Are these GPIO Pins or FMC pins?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

pmod, I saw Arty one used pmod, so I mapped these to nexysvideo's pmod JA/JB pins.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I see.

Can you also push a version that maps it to FMC?

case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
harnessIO <> port.io

harnessIO match {
case io: DecoupledPhitIO => {
val clkIO = io match {
case io: InternalSyncPhitIO => IOPin(io.clock_out)
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
}
val packagePinsWithPackageIOs = Seq(
("AB22", clkIO),
("AB21", IOPin(io.out.valid)),
("AB20", IOPin(io.out.ready)),
("AB18", IOPin(io.in.valid)),
("Y21", IOPin(io.in.ready)),
("AA21", IOPin(io.out.bits.phit, 0)),
("AA20", IOPin(io.out.bits.phit, 1)),
("AA18", IOPin(io.out.bits.phit, 2)),
("V9", IOPin(io.out.bits.phit, 3)),
("V8", IOPin(io.in.bits.phit, 0)),
("V7", IOPin(io.in.bits.phit, 1)),
("W7", IOPin(io.in.bits.phit, 2)),
("W9", IOPin(io.in.bits.phit, 3))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
nexysTh.xdc.addPackagePin(io, pin)
nexysTh.xdc.addIOStandard(io, "LVCMOS33")
}}

// Don't add IOB to the clock, if its an input
io match {
case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
nexysTh.xdc.addIOB(io)
}}
case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
nexysTh.xdc.addIOB(io)
}}
}

nexysTh.sdc.addClock("ser_tl_clock", clkIO, 100)
nexysTh.sdc.addGroup(pins = Seq(clkIO))
nexysTh.xdc.clockDedicatedRouteFalse(clkIO)
}
}
}
})

Loading