ucb-bar · jwright6323 · Feb 14, 2019 · Feb 7, 2019 · Feb 13, 2019
diff --git a/.gitmodules b/.gitmodules
@@ -4,3 +4,6 @@
 [submodule "testchipip"]
 	path = testchipip
 	url = https://github.com/ucb-bar/testchipip.git
+[submodule "barstools"]
+	path = barstools
+	url = git@github.com:ucb-bar/barstools
diff --git a/Makefrag b/Makefrag
@@ -1,13 +1,16 @@
 ROCKETCHIP_DIR=$(base_dir)/rocket-chip
 
-SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4
+SCALA_VERSION=2.12.4
+SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
+
+SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
 
 lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
 
 PACKAGES=rocket-chip testchipip
 SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
 
-ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-2.12/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.12/*"
+ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
 FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver
 
@@ -24,16 +27,47 @@ include $(testchip_dir)/Makefrag
 
 CHISEL_ARGS ?=
 
-FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
-ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json
-VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
+long_name=$(PROJECT).$(MODEL).$(CONFIG)
+
+FIRRTL_FILE  ?=$(build_dir)/$(long_name).fir
+ANNO_FILE    ?=$(build_dir)/$(long_name).anno.json
+VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
+HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
+SMEMS_FILE   ?=$(build_dir)/$(long_name).mems.v
+SMEMS_CONF   ?=$(build_dir)/$(long_name).mems.conf
+
+REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
+
+# This should match whatever the commonSettings version is in build.sbt
+BARSTOOLS_VER=1.0
+TAPEOUT_JAR=$(base_dir)/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout_$(SCALA_VERSION_MAJOR)-$(BARSTOOLS_VER).jar
+MACROCOMPILER_JAR=$(base_dir)/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
+
+TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR):$(TAPEOUT_JAR)
+MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR):$(MACROCOMPILER_JAR)
+
+$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/tapeout/src/main/scala) $(FIRRTL_JAR)
+	cd $(base_dir) && $(SBT) "tapeout/package"
+
+$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/barstools/mdf/scalalib/src/main/scala) $(FIRRTL_JAR)
+	cd $(base_dir) && $(SBT) "barstools-macros/assembly"
+
+.PHONY: jars
+jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
 
 $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
-$(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR)
-	$(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE)
+$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
+	$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM)
+
+$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
+	$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE)
+
+# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
+$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)
+	$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops
 
 regression-tests = \
 	rv64ud-v-fcvt \

diff --git a/barstools b/barstools
diff --git a/build.sbt b/build.sbt
@@ -3,10 +3,15 @@ lazy val commonSettings = Seq(
   version := "1.0",
   scalaVersion := "2.12.4",
   traceLevel := 15,
+  test in assembly := {},
+  assemblyMergeStrategy in assembly := { _ match {
+    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
+    case _ => MergeStrategy.first}},
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
   libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test",
   libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3",
   libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+  libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT",
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
@@ -15,6 +20,21 @@ lazy val commonSettings = Seq(
 
 lazy val rocketchip = RootProject(file("rocket-chip"))
 
-lazy val testchipip = project.settings(commonSettings).dependsOn(rocketchip)
+lazy val testchipip = project.settings(commonSettings)
+  .dependsOn(rocketchip)
+
+lazy val example = (project in file("."))
+  .settings(commonSettings)
+  .dependsOn(testchipip)
+
+lazy val tapeout = (project in file("./barstools/tapeout/"))
+  .settings(commonSettings)
+  .dependsOn(rocketchip)
+
+lazy val mdf = (project in file("./barstools/mdf/scalalib/"))
+
+lazy val `barstools-macros` = (project in file("./barstools/macros/"))
+  .enablePlugins(sbtassembly.AssemblyPlugin)
+  .settings(commonSettings)
+  .dependsOn(rocketchip, mdf)
 
-lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip)
diff --git a/project/build.properties b/project/build.properties
@@ -0,0 +1 @@
+sbt.version=1.2.7
diff --git a/project/plugins.sbt b/project/plugins.sbt
@@ -0,0 +1 @@
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
diff --git a/testchipip b/testchipip
diff --git a/verisim/Makefile b/verisim/Makefile
@@ -6,6 +6,7 @@ MODEL ?= TestHarness
 CONFIG ?= DefaultExampleConfig
 CFG_PROJECT ?= $(PROJECT)
 TB ?= TestDriver
+TOP ?= ExampleTop
 
 sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
 sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
@@ -20,12 +21,12 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag-verilator
 
-long_name = $(PROJECT).$(MODEL).$(CONFIG)
-
 rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 
 sim_vsrcs = \
-	$(build_dir)/$(long_name).v \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE) \
 	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
 	$(rocketchip_vsrc_dir)/plusarg_reader.v \
 	$(testchip_vsrcs)
@@ -47,7 +48,7 @@ $(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(model_header)"
 	touch $@
 

diff --git a/verisim/Makefrag-verilator b/verisim/Makefrag-verilator
@@ -29,9 +29,8 @@ rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 VERILATOR_FLAGS := --top-module $(MODEL) \
-  +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-  +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-  --output-split 20000 \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+	--output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
-  -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"
+	-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"
diff --git a/vsim/Makefile b/vsim/Makefile
@@ -6,6 +6,7 @@ MODEL ?= TestHarness
 CONFIG ?= DefaultExampleConfig
 CFG_PROJECT ?= $(PROJECT)
 TB ?= TestDriver
+TOP ?= ExampleTop
 
 simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
 simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
@@ -19,7 +20,9 @@ include $(base_dir)/Makefrag
 rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 
 sim_vsrcs = \
-	$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE) \
 	$(rocketchip_vsrc_dir)/TestDriver.v \
 	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
 	$(rocketchip_vsrc_dir)/plusarg_reader.v \
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
+1 −0		Makefrag
+3 −3		csrc/blkdev.cc
+2 −2		csrc/blkdev.h
+177 −0		src/main/scala/ClockUtil.scala
+131 −0		src/main/scala/ClockUtilTests.scala
+2 −1		src/main/scala/Serdes.scala
+2 −1		src/main/scala/Unittests.scala
+130 −0		vsrc/ClockUtil.v