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Line coverage report fails with VerilatorBackend

bugSomething isn't workingSomething isn't working

Status: Open.

#735 In ucb-bar/chiseltest;

· PhilippKasgen opened on Jun 28, 2024

Implement SytemVerilog style Sequences

Status: Open.

#733 In ucb-bar/chiseltest;

· Gallagator opened on Jun 17, 2024

Cover is not yet implemented for Chiseltest

Status: Open.

#732 In ucb-bar/chiseltest;

· Gallagator opened on Jun 17, 2024

Solver Chosen Constants for Formal Verification

Status: Open.

#664 In ucb-bar/chiseltest;

· fayalalebrun opened on Aug 6, 2023

Report assert message with <code>FailedBoundedCheckException</code>

Status: Open.

#652 In ucb-bar/chiseltest;

· yupferris opened on Jun 30, 2023

JRE detects <code>EXCEPTION_ACCESS_VIOLATION</code> when trying to use Verilator as Chiseltest's backend

Status: Open.

#649 In ucb-bar/chiseltest;

· hiroshi-ya opened on Jun 25, 2023

Proving formal properties

Status: Open.

#648 In ucb-bar/chiseltest;

· yupferris opened on Jun 20, 2023

Checking formal properties over multiple tests

Status: Open.

#647 In ucb-bar/chiseltest;

· yupferris opened on Jun 20, 2023

<code>poke</code> in <code>ChiselScalatestTester</code> occurs on falling clock edge in traces

Status: Open.

#646 In ucb-bar/chiseltest;

· yupferris opened on Jun 19, 2023

TODO: implement plusarg intrinsic support for all supported simulators and formal verification

Status: Open.

#638 In ucb-bar/chiseltest;

· ekiwi opened on Jun 9, 2023

Confused by fork.withRegion(Monitor)

Status: Open.

#630 In ucb-bar/chiseltest;

· mvanbeirendonck opened on Apr 25, 2023

Confusing Fork-Join Usage

Status: Open.

#627 In ucb-bar/chiseltest;

· liuxd17thu opened on Mar 28, 2023