Merge Dev Into Master #171
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* wip load/store * created & parameterized bundles * fix config ex rs1 * optimize loopconv & loopmatmul with bundles; add bundles for preload and compute * move assignments to pipeline output Co-authored-by: Ruohan Yan <yrh@a5.Millennium.Berkeley.EDU>
Added new convenience scripts and config files
By default, there will be just one TLB shared by both the read and write DMAs
* Support single-porting accumulator through the use of accumulator "sub-banks" * Support clock-gating Gemmini modules * Support sharing SPAD/ACC between Int8 and FP gemminis * Reduce bitwidths of loop unroller multipliers and adders * Fix error where small portion of scratchpad was unusable when double-buffering in the loop unrollers When single-porting the accumulator banks, input-dilated convs will sometimes fail because they keep writing to the same accumulator banks. A different write pattern will have to be found eventually for those cases, but that's outside the scope of this PR.
Also, make it easier to pipeline reduction trees by pipelining tiles rather than PEs
We add a new experimental "pixel_repeats" feature to optimize conv layers with few input channels (like the first layer of most CNNs).
* Reduce a few bitwidths in ReservationStation.scala
Fixes bug where TLB hits were being counted incorrectly. Prior to this PR, we were using RegNext(io.req.fire()) to match TLB requests to TLB responses. However, we made our interface to the TLB combinational months ago, so the RegNext is no longer necessary (and is actually incorrect).
…ementations (#169) Rename tiled_conv_A_stride to tiled_conv and cleanup unused conv implementations
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