Ci cd debug #670
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Ci cd debug #670
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Co-authored-by: Harrison Liew <harrisonliew@gmail.com>
Co-authored-by: Harrison Liew <harrisonliew@gmail.com>
- Update typing-related code for newer Python/mypy
- Old pyyaml uses dead code
File "/buildbot/run_unittests/build/src/tools/pyyaml/lib3/yaml/constructor.py", line 126, in construct_mapping
if not isinstance(key, collections.Hashable):
AttributeError: module 'collections' has no attribute 'Hashable'
* magic DRC works * hier DRC count doesn't work in batch mode, LVS runs but layout -> spice extraction fails with Illegal overlap (types to not connect) error * type checking * move .ext files into separate rundir * extract improvements but still bad netlist * clarify some comments
@odxa20 reported in ucb-bar/chipyard#1173 that an X-to-Y step caused an BlockingIOError. Replacing printing the entire output config to stdout with just a message pointing to where the output config was written solves this + makes Hammer much less verbose.
* added a few imports * adding synthesis.yosys.binary key * splitting sky130 tiehilocell into tiehicell and tielocell * first pass on Yosys plugin, based on OpenLANE TCL scripts * cleaned up plugin, manually write sdc file * finished basic RTL to GDS flow for openroad plugin * adding klayout technology file * adding openroad-specific files for sky130 * adding openroad-specific files for sky130 * sky130 plugin modifications for openroad * yosys plugin * hammer changes to support openroad/yosys * implemented open_chip script and starting at a par step, cleaned up many things * openroad pnr fails at write gds step, something wrong with klayout settings * fixes from PR comments, chipyard design runs through synthesis * sky130 plugin updates to support openroad + new PDK updates * adding mypy tests, changed buffer to driver * small changes * openroad pnr flow complete (write GDS works) * cleaned up openroad plugin * removed hard-coded paths and other cleanup * removed hard-coded cell names * clarified unit conversion * removing more hard-coded values * place pins side functionality, hook for set wire rc * fixes for unit tests * fixed most of tests, def2stream.py is failing * seems to be passing all tests * excluding def2stream.py from mypy tests * fixing special cells test
* Update defaults_types.yml Changed default type of vlsi.core.node to int from str since in all the technology files defaults.yml the value is an int. Without this change the following error arises Expected primary type str for vlsi.core.node, got type int * Update defaults.yml Changed default vlsi.core.node to conform with recently implemented type checks
`vlsi.core.technology` is a str and `vlsi.core.node` is an int
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Testing bash tests again for github acitons