Merge pull request #42 from ucb-bar/scala213

[WIP] Bump to scala 2.13/chisel 3.5.5/new rocketchip

build.sbt

@@ -4,4 +4,4 @@ version := "1.2"
 
 name := "hwacha"
 
-scalaVersion := "2.12.10"
+scalaVersion := "2.13.10"

src/main/scala/TopLevelConfigs.scala

@@ -18,14 +18,17 @@ class WithNLanes(n: Int) extends Config((site, here, up) => {
 })
 
 class With32BtbEntires extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
-    r.copy(btb = r.btb.map(_.copy(nEntries = 32)))
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      btb = tp.tileParams.btb.map(_.copy(nEntries = 32))))
   }
 })
 
 class Process28nmConfig extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
-    r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(sfmaLatency = 3, dfmaLatency = 4))))
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(
+        fpu = tp.tileParams.core.fpu.map(_.copy(sfmaLatency = 3, dfmaLatency = 4)))))
   }
 })
 

src/main/scala/dcc-mem.scala

@@ -128,7 +128,7 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic {
   opq.suggestName("opqInst")
   opq.io.enq <> io.op
 
-  val bpqs = (io.bpqs zipWithIndex) map { case (enq, i) =>
+  val bpqs = (io.bpqs.zipWithIndex) map { case (enq, i) =>
     val bpq = Module(new Queue(new BPQEntry, nBPQ))
     bpq.suggestName("bpqInst")
     val placntr = Module(new LookAheadCounter(nBPQ, nBPQ))
@@ -152,7 +152,7 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic {
   val vlen_next = op.vlen - strip
 
   val deq_bpqs = strip_to_bmask(strip)
-  val mask_bpqs_valid = (bpqs_deq zipWithIndex) map { case (bpq, i) =>
+  val mask_bpqs_valid = (bpqs_deq.zipWithIndex) map { case (bpq, i) =>
     !deq_bpqs(i) || bpq.valid }
   val enq_lpred = op.active.enq_vlu()
   val enq_spred = op.active.enq_vsu()
@@ -187,13 +187,13 @@ class VPU(implicit p: Parameters) extends VXUModule()(p) with BankLogic {
     }
   }
 
-  (bpqs_deq zipWithIndex) map { case (bpq, i) =>
+  (bpqs_deq.zipWithIndex) map { case (bpq, i) =>
     bpq.ready := fire(mask_bpqs_valid(i), deq_bpqs(i)) }
   io.pred.valid := fire(io.pred.ready)
   io.lpred.valid := fire(mask_lpred_ready, enq_lpred)
   io.spred.valid := fire(mask_spred_ready, enq_spred)
 
-  val pred = Vec((bpqs_deq zipWithIndex) map { case (bpq, i) =>
+  val pred = Vec((bpqs_deq.zipWithIndex) map { case (bpq, i) =>
     dgate(deq_bpqs(i), bpq.bits.pred(nSlices-1,0)) }).asUInt
   io.pred.bits.pred := pred
   io.lpred.bits := pred

src/main/scala/expander.scala

@@ -185,7 +185,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) {
     }
 
     def mark_sram_reads = {
-      (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) foreach {
+      (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) foreach {
         case (fn, idx) => {
           val read_idx = rport_idx(idx)
           when (rport_valid(idx)) {
@@ -415,7 +415,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) {
     }
 
     def mark_lop_sreg(sreg: Vec[Bool], nregs: Int) = {
-      (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) map { case (fn, i) =>
+      (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) map { case (fn, i) =>
         if (nregs > i) {
           val rinfo = fn(seq_exp.reg)
           sreg(i) := rinfo.valid && rinfo.is_scalar()
@@ -441,7 +441,7 @@ class Expander(implicit p: Parameters) extends VXUModule()(p) {
       (lop: VFVULaneOp) => { lop.fn := seq_exp.fn.vfvu(); mark_lop_sreg(lop.sreg, 1) })
 
     def mark_vipu = {
-      (Seq(preg_vs1, preg_vs2, preg_vs3) zipWithIndex) foreach { case (fn, idx) =>
+      (Seq(preg_vs1, preg_vs2, preg_vs3).zipWithIndex) foreach { case (fn, idx) =>
         check_assert("pred read" + idx, tick_pred_read(idx), UInt(0))
         assert(fn(seq_vipu.reg).valid, "pred op with no predicate")
         val e = tick_pred_read(idx).s(0)

src/main/scala/hwacha.scala

@@ -39,7 +39,9 @@ abstract class HwachaModule(clock: Clock = null, _reset: Bool = null)
 abstract class HwachaBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
   with UsesHwachaParameters
 
-abstract trait UsesHwachaParameters extends freechips.rocketchip.tile.HasCoreParameters with UsesHwachaOnlyParameters
+abstract trait UsesHwachaParameters extends freechips.rocketchip.tile.HasCoreParameters with UsesHwachaOnlyParameters {
+  val aluFn = new freechips.rocketchip.rocket.ALUFN
+}
 
 abstract trait UsesHwachaOnlyParameters {
   implicit val p: Parameters
@@ -250,7 +252,7 @@ class HwachaImp(outer: Hwacha)(implicit p: Parameters) extends LazyRoCCModuleImp
 
   mseq.io.op.valid := fire_vxu(mseq.io.op.ready)
   mseq.io.op.bits <> scalar.io.vxu.bits
-  (mseq.io.master.clear zipWithIndex) map { case (c, r) =>
+  (mseq.io.master.clear.zipWithIndex) map { case (c, r) =>
     c := vus.map(_.io.mseq.clear(r)).reduce(_&&_)
   }
   scalar.io.pending.mseq <> mseq.io.pending
@@ -273,7 +275,7 @@ class HwachaImp(outer: Hwacha)(implicit p: Parameters) extends LazyRoCCModuleImp
   (vus zip mou.io.check.vus) map { case (vu, mocheck) => vu.io.mocheck <> mocheck }
   (scalar.io.pending.mrt.vus zip vus) map { case (pending, vu) => pending <> vu.io.pending }
 
-  (vus zipWithIndex) map { case (vu, i) =>
+  (vus.zipWithIndex) map { case (vu, i) =>
     vu.io.id := UInt(i)
 
     vu.io.cfg <> rocc.io.cfg

src/main/scala/lane.scala

@@ -307,7 +307,7 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
   banksrw.map { b =>
     b.wpred.pred := Vec(vfcus.map(_.bits.cmp)).asUInt
     b.wpred.mask := vfcu_vals
-    (b.wdata zipWithIndex) map { case (bwdata, i) =>
+    (b.wdata.zipWithIndex) map { case (bwdata, i) =>
       bwdata.data := wdata(i)
       bwdata.pred := wdata_pred(i)
     }