Merge pull request #9 from SingularityKChen/master

fix: chisel3 pr #2758

src/main/scala/freechips/rocketchip/amba/axi4stream/AXI4StreamModel.scala

@@ -1,7 +1,7 @@
 package freechips.rocketchip.amba.axi4stream
 
 import breeze.stats.distributions._
-import chisel3.MultiIOModule
+import chisel3.Module
 import chisel3.iotesters.PeekPokeTester
 
 import scala.language.implicitConversions

src/main/scala/freechips/rocketchip/amba/axi4stream/AXI4StreamWidthAdapter.scala

@@ -116,7 +116,7 @@ object AXI4StreamWidthAdapter {
 
   def nToOneOrAdapater(n: Int): AdapterFun = (u, iv, or) => {
     val cat = nToOneCatAdapter(n)(u, iv, or)
-    (cat._1.orR(), cat._2, cat._3)
+    (cat._1.orR, cat._2, cat._3)
   }
 
   def nToOne(n: Int): AXI4StreamAdapterNode =

src/main/scala/freechips/rocketchip/jtag2mm/JtagShifter.scala

@@ -103,7 +103,7 @@ class CaptureChain[+T <: Data](gen: T) extends Chain {
   io.chainOut.data := regs(0)
 
   when(io.chainIn.capture) {
-    (0 until n).map(x => regs(x) := io.capture.bits.asUInt()(x))
+    (0 until n).map(x => regs(x) := io.capture.bits.asUInt(x))
     io.capture.capture := true.B
   }.elsewhen(io.chainIn.shift) {
     regs(n - 1) := io.chainIn.data
@@ -164,7 +164,7 @@ class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V) ex
     io.update.bits := 0.U
   }
 
-  val captureBits = io.capture.bits.asUInt()
+  val captureBits = io.capture.bits.asUInt
 
   when(io.chainIn.capture) {
     (0 until math.min(n, captureWidth)).map(x => regs(x) := captureBits(x))

src/main/scala/freechips/rocketchip/jtag2mm/TestMultiplexer.scala

@@ -3,7 +3,7 @@
 package freechips.rocketchip.jtag2mm
 
 import chisel3._
-import chisel3.experimental._
+//import chisel3.experimental._
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import dspblocks._

src/test/scala/dsptools/tester/MemMasterSpec.scala

@@ -120,7 +120,7 @@ class APBRegmapExample extends APBRegisterRouter(0,
 }
 
 class MemMasterSpec extends AnyFlatSpec with Matchers {
-  abstract class RegmapExampleTester[M <: MultiIOModule](c: M) extends PeekPokeTester(c) with MemMasterModel {
+  abstract class RegmapExampleTester[M <: Module](c: M) extends PeekPokeTester(c) with MemMasterModel {
     memReadWord(0x00) should be (0)
     memReadWord(0x08) should be (1)
     memReadWord(0x10) should be (0)