Bump to scala 2.13/chisel 3.5.5/latest rocketchip

build.sbt

@@ -4,9 +4,7 @@ version := "1.0-SNAPSHOT"
 
 name := "testchipip"
 
-scalaVersion := "2.12.10"
-
-scalacOptions += "-Xsource:2.11"
+scalaVersion := "2.13.10"
 
 libraryDependencies += "edu.berkeley.cs" %% "rocketchip" % "1.2.+"
 

src/main/scala/Serdes.scala

@@ -515,7 +515,8 @@ class TLSerdes(w: Int, params: Seq[TLManagerParameters], beatBytes: Int = 8, has
         managers = Seq(manager),
         beatBytes = beatBytes)))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val nChannels = params.size
     val io = IO(new Bundle {
       val ser = Vec(nChannels, new SerialIO(w))
@@ -555,7 +556,8 @@ class TLDesser(w: Int, params: Seq[TLClientParameters], hasCorruptDenied: Boolea
   val node = TLClientNode(params.map(client =>
       TLMasterPortParameters.v1(Seq(client))))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val nChannels = params.size
     val io = IO(new Bundle {
       val ser = Vec(nChannels, new SerialIO(w))
@@ -601,7 +603,8 @@ class TLSerdesser(
   val clientNode = TLClientNode(Seq(clientPortParams))
   val managerNode = TLManagerNode(Seq(managerPortParams))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val ser = new SerialIO(w)
     })

src/main/scala/SerialAdapter.scala

@@ -471,7 +471,8 @@ class SerialRAM(
 
   serdesser.managerNode := TLBuffer() := adapter.node
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val ser = Flipped(new SerialIO(w))
       val tsi_ser = new SerialIO(SERIAL_TSI_WIDTH)
@@ -570,11 +571,12 @@ class MultiClockSerialAXIRAM(
       port.clock := memClkRstSource.out.head._1.clock
       port.reset := memClkRstSource.out.head._1.reset
       port
-    })
+    }).toSeq
     ports
   }
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val ser = Flipped(new SerialIO(w))
       val tsi_ser = new SerialIO(SERIAL_TSI_WIDTH)

src/main/scala/Switcher.scala

@@ -123,7 +123,8 @@ class TLSwitcher(
         name = s"switch_$i", sourceId = IdRange(0, 1 << idBits))))
     })): Seq[TLClientNode]
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val sel = Input(UInt(log2Ceil(outPortN.size).W))
     })

src/main/scala/TileResetCtrl.scala

@@ -45,7 +45,7 @@ class TLTileResetCtrl(w: Int, params: TileResetCtrlParams, tile_prci_domains: Se
       }
     })
     node.regmap((0 until nTiles).map({ i =>
-      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)),
+      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
     }): _*)
 
     val tileMap = tile_prci_domains.zipWithIndex.map({ case (d, i) =>

src/main/scala/Unittests.scala

@@ -16,7 +16,8 @@ class BlockDeviceTrackerTestDriver(nSectors: Int)(implicit p: Parameters)
   val node = TLHelper.makeClientNode(
     name = "blkdev-testdriver", sourceId = IdRange(0, 1))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val start = Input(Bool())
       val finished = Output(Bool())
@@ -156,7 +157,8 @@ class SerdesTest(implicit p: Parameters) extends LazyModule {
   testram.node := TLBuffer() :=
     TLFragmenter(beatBytes, lineBytes) := desser.node
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle { val finished = Output(Bool()) })
 
     val mergeType = serdes.module.mergeTypes(0)
@@ -346,7 +348,8 @@ class SwitcherTest(implicit p: Parameters) extends LazyModule {
     TLFragmenter(beatBytes, lineBytes) :=
     switcher.outnodes(1))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle with UnitTestIO)
 
     io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _)
@@ -381,7 +384,8 @@ class TLRingNetworkTest(implicit p: Parameters) extends LazyModule {
   fuzzers.foreach(ring.node := _.node)
   rams.foreach(_.node := TLFragmenter(beatBytes, blockBytes) := ring.node)
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle with UnitTestIO)
 
     io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _)

src/main/scala/tsiHost/TsiHostWidget.scala

@@ -164,7 +164,8 @@ class TLTSIHostBackend(val params: TSIHostParams)(implicit p: Parameters)
   // create TL node to connect to outer bus
   val externalClientNode = serdes.clientNode
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val adapterSerial = new SerialIO(SerialAdapter.SERIAL_TSI_WIDTH)
       val serdesSerial =  new SerialIO(params.offchipSerialIfWidth)
@@ -232,7 +233,8 @@ class TLTSIHostWidget(val beatBytes: Int, val params: TSIHostParams)(implicit p:
   // io node handle to create source and sink io's
   val ioNode = BundleBridgeSource(() => new TSIHostWidgetIO(params.offchipSerialIfWidth))
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = ioNode.bundle
 
     val backendMod = backend.module

src/main/scala/tsiHost/TsiHostWidgetUnitTest.scala

@@ -50,7 +50,8 @@ class TSIHostWidgetBackendTest(implicit p: Parameters) extends LazyModule {
   hostRam.node := TLFragmenter(systemBeatBytes, targetLineBytes) := TLBuffer() := hostTSIHostWidgetBackend.externalClientNode
 
   // implementation of the module
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     // i/o to connect to the unit test interface
     val io = IO(new Bundle with UnitTestIO)
 
@@ -164,7 +165,8 @@ class TSIHostWidgetTest(implicit p: Parameters) extends LazyModule {
   val tsiHostIOSink = hostTSIHostWidget.ioNode.makeSink
 
   // implementation of the module
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     // i/o to connect to the unit test interface
     val io = IO(new Bundle with UnitTestIO)