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Verilog: fill typeref fields of instances #3470

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This one is conceptually based on
master...my2817:ctags:master
reported and written by @my2817 at #3469.

The test case is also taken from #3469 submitted by @my2817.

This commit does two things:

  • fill typeref fields of instances with module names, and
  • extract the module names used for defining instances as
    defInstance role of module kind.

TODO: Update ctags-lang-verilog(7).

This one is conceptually based on
universal-ctags/ctags@master...my2817:ctags:master
reported and written by @my2817 at universal-ctags#3469.

The test case is also taken from universal-ctags#3469 submitted by @my2817.

This commit does two things:

* fill typeref fields of instances with module names, and
* extract the module names used for defining instances as
  defInstance role of module kind.

TODO: Update ctags-lang-verilog(7).
@@ -1409,7 +1434,7 @@ static int processAssertion (tokenInfo *const token, int c)

// data_declaration ::=
// ...
// import < package_identifier :: identifier | package_identifier :: * > ;
// import < package_identifier :: identifier | package_identifier :: * > ;
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This change is not needed.

@masatake
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This pull request proposed two things. To simplify the discussion and review process, I made a new pull request that focused only on one of two. See #3471.

I will rework this pull request after #3471 is merged.

@masatake masatake closed this Aug 26, 2022
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