Verilog: extract module names used for defining instances as reference tags #3473
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I see. I will update the name of the role. I will keep this draft till I write about |
masatake
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I see. |
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The man page is updated. |
docs/man/ctags-lang-verilog.7.rst
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| Supported Roles | ||
| ~~~~~~~~~~~~~~~ | ||
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| .. warning:: | ||
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| The support for references in Universal Ctags is still | ||
| experimental; the names of the roles can be changed in the future. | ||
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| .. code-block:: console | ||
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| $ ./ctags --list-roles=SystemVerilog | ||
| #KIND(L/N) NAME ENABLED DESCRIPTION | ||
| m/module decl on declaring instances | ||
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| $ ./ctags --list-roles=Verilog | ||
| #KIND(L/N) NAME ENABLED DESCRIPTION | ||
| m/module decl on declaring instances | ||
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| The parsers extract modules names used in instance declarations as | ||
| reference tags. ``decl`` is the role for the names. See "TAG ENTRIES" | ||
| section of :ref:`ctags(1) <ctags(1)>` about reference tags and roles. | ||
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This is not the output from ctags-lang-verilog.7.rst.in.
This is a true fail.
man/ctags-lang-verilog.7.rst.in
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| The parsers extract modules names used in instance declarations as | ||
| reference tags. ``decl`` is the role for the tags. See "TAG ENTRIES" |
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How about:
The parser extracts module-names (or names of modules) used in instance declarations as reference tags.
We can say "The parsers extraces ...". If we choose this, we have to change other sentences in this manual.
The man page about SystemVerilog/Verilog parsers for Universal Ctags
This man page describes about the SystemVerilog/Verilog parsers for Universal Ctags.
I prefer singulars.
…ce tags This one is conceptually based on universal-ctags/ctags@master...my2817:ctags:master reported and written by @my2817 at universal-ctags#3469. The test case is also taken from universal-ctags#3469 submitted by @my2817.
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This one is conceptually based on
master...my2817:ctags:master
reported and written by @my2817 at #3469.
The test case is also taken from #3469 submitted by @my2817.