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fix overlapping prep timers #129

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elgarten
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Previously, timer outputs from separate PXNs would overlap, making the output unusable. Adds a simple barrier to ensure each PXN waits for its turn when logging timer info.

@elgarten elgarten requested a review from tewaro July 18, 2024 16:21
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Please add the same changes for drvx

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Superseded by #137.

@elgarten elgarten closed this Jul 30, 2024
elgarten added a commit that referenced this pull request Aug 12, 2024
…#127 + #129) (#137)

* Fix hang in TC microbenchmark

Added a shared WaitGroup between vertex doAll and the nested, per vertex,
edge doAll. Original code would hang because of the separate wait groups:
after enqueueing a doAll in edge_tc_couting, harts wait for it to complete
(tc_algos.cpp:42). However, this occurs on every hart because of the outer
doAll in tc_no_chunk, therefore every hart is waiting and none is available
to complete the work being waited on. When using one combined wait group,
the outer doAll tasks are able to complete after enqueuing, but before
completion of, the inner doAll tasks. Thus, harts are freed to complete the
inner doAll and therefore forward progress.

* fix overlapping prep timers

* add synchronization to drv timers
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2 participants