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Refactor: rearranged X86 files.
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@uxmal
uxmal committed Sep 4, 2023
1 parent a0e1b44 commit 04ffec4
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Showing 44 changed files with 1,048 additions and 1,335 deletions.
1 change: 1 addition & 0 deletions src/Arch/X86/Analysis/FstswAnalysis.cs
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Expand Up @@ -19,6 +19,7 @@
#endregion

using Reko.Analysis;
using Reko.Arch.X86.Rewriter;
using Reko.Core;
using Reko.Core.Code;
using Reko.Core.Collections;
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4 changes: 2 additions & 2 deletions src/Arch/X86/X86FrameApplicationBuilder.cs → ...86/Analysis/X86FrameApplicationBuilder.cs
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Expand Up @@ -28,13 +28,13 @@
using Reko.Core.Operators;
using Reko.Core.Analysis;

namespace Reko.Arch.X86
namespace Reko.Arch.X86.Analysis
{
public class X86FrameApplicationBuilder : FrameApplicationBuilder
{
public X86FrameApplicationBuilder(
IntelArchitecture arch,
IStorageBinder binder,
IStorageBinder binder,
CallSite site)
: base(arch, binder, site)
{
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0 src/Arch/X86/InstructionSet.cs → src/Arch/X86/Disassembler/InstructionSet.cs
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0 src/Arch/X86/X86Disassembler.0F38.cs → .../X86/Disassembler/X86Disassembler.0F38.cs
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0 src/Arch/X86/X86Disassembler.0F3A.cs → .../X86/Disassembler/X86Disassembler.0F3A.cs
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0 src/Arch/X86/X86Disassembler.Decoders.cs → .../Disassembler/X86Disassembler.Decoders.cs
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0 src/Arch/X86/X86Disassembler.Groups.cs → ...86/Disassembler/X86Disassembler.Groups.cs
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0 src/Arch/X86/X86Disassembler.OneByte.cs → ...6/Disassembler/X86Disassembler.OneByte.cs
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0 src/Arch/X86/X86Disassembler.TwoByte.cs → ...6/Disassembler/X86Disassembler.TwoByte.cs
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0 src/Arch/X86/X86Disassembler.cs → src/Arch/X86/Disassembler/X86Disassembler.cs
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0 src/Arch/X86/X86Disassembler.x87.cs → ...h/X86/Disassembler/X86Disassembler.x87.cs
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126 changes: 63 additions & 63 deletions src/Arch/X86/X86Emulator.cs → src/Arch/X86/Emulator/X86Emulator.cs
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Expand Up @@ -30,9 +30,9 @@
using System.Runtime.CompilerServices;
using System.Text;

namespace Reko.Arch.X86
namespace Reko.Arch.X86.Emulator
{
using TWord = System.UInt32;
using TWord = UInt32;

/// <summary>
/// Simple emulator of X86 instructions. No attempt is made to be high-performance
Expand All @@ -47,12 +47,12 @@ public abstract class X86Emulator : EmulatorBase
public const uint Dmask = 1u << 10;
public const uint Omask = 1u << 11;

protected static readonly TraceSwitch trace = new TraceSwitch(nameof(X86Emulator), "Trace execution of X86 Emulator")
{
protected static readonly TraceSwitch trace = new TraceSwitch(nameof(X86Emulator), "Trace execution of X86 Emulator")
{
Level = TraceLevel.Warning
};

public static readonly (uint value, uint hibit)[] masks = new(uint, uint)[]{
public static readonly (uint value, uint hibit)[] masks = new (uint, uint)[]{
(0, 0),
(0x0000_00FFu, 0x0000_0080),
(0x0000_FFFFu, 0x0000_8000),
Expand Down Expand Up @@ -87,22 +87,22 @@ public X86Emulator(
: base(segmentMap)
{
this.arch = arch;
this.map = segmentMap;
map = segmentMap;
this.ipReg = ipReg;
this.cxReg = cxReg;
this.Registers = new ulong[40];
this.iFlags = X86.Registers.eflags.Number;
Registers = new ulong[40];
iFlags = X86.Registers.eflags.Number;
this.envEmulator = envEmulator;
this.dasm = default!;
this.ip = default!;
dasm = default!;
ip = default!;
}

public override MachineInstruction CurrentInstruction => dasm.Current;

public ulong Flags
{
get { return this.Registers[iFlags]; }
set { this.Registers[iFlags] = value; }
get { return Registers[iFlags]; }
set { Registers[iFlags] = value; }
}

public abstract Address AddressFromWord(ulong word);
Expand All @@ -126,8 +126,8 @@ public override Address InstructionPointer
[MethodImpl(MethodImplOptions.AggressiveInlining)]
private void UpdateIp(Address value)
{
this.ip = value;
WriteRegister(this.ipReg, (TWord) value.Offset);
ip = value;
WriteRegister(ipReg, (TWord) value.Offset);
if (value.Selector.HasValue)
{
WriteRegister(X86.Registers.cs, value.Selector.Value);
Expand Down Expand Up @@ -274,7 +274,7 @@ protected TWord GetEffectiveOffset(MemoryOperand m)
if (m.Offset != null)
ea += m.Offset.ToUInt32();
if (m.Index != RegisterStorage.None)
ea += (TWord)ReadRegister(m.Index) * m.Scale;
ea += (TWord) ReadRegister(m.Index) * m.Scale;
if (m.Base != null && m.Base != RegisterStorage.None)
{
ea += (TWord) ReadRegister(m.Base);
Expand Down Expand Up @@ -335,7 +335,7 @@ private void Write(MachineOperand op, TWord w)

public sealed override ulong WriteRegister(RegisterStorage r, ulong value)
{
Registers[r.Number] = (Registers[r.Number] & ~r.BitMask) | (value << (int) r.BitAddress);
Registers[r.Number] = Registers[r.Number] & ~r.BitMask | value << (int) r.BitAddress;
return value;
}

Expand All @@ -345,7 +345,7 @@ public void WriteMemory(TWord w, ulong ea, DataType dt)
{
case 1: WriteByte(ea, (byte) w); return;
case 2: WriteLeUInt16(ea, (ushort) w); return;
case 4: WriteLeUInt32(ea, (uint) w); return;
case 4: WriteLeUInt32(ea, w); return;
case 8: throw new NotImplementedException();
}
throw new InvalidOperationException();
Expand Down Expand Up @@ -374,18 +374,18 @@ private void Adc(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
TWord r = Read(src);
var mask = masks[dst.Width.Size];
TWord sum = (l + r + ((uint)Flags & 1)) & mask.value;
TWord sum = l + r + ((uint) Flags & 1) & mask.value;
Write(dst, sum);
var newCy =
((l & r) | ((l | r) & (~(sum)))) >> 31;
(l & r | (l | r) & ~sum) >> 31;

uint ov = ((~(l ^ r) & (l ^ sum)) & 0x80000000u) >> 20;
uint ov = (~(l ^ r) & (l ^ sum) & 0x80000000u) >> 20;
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
(newCy) | // Carry
newCy | // Carry
(sum == 0 ? 1u << 6 : 0u) | // Zero
((sum & mask.hibit) != 0 ? Smask : 0u) | // Sign
(ov) // Overflow
ov // Overflow
;
}

Expand All @@ -396,37 +396,37 @@ private void Add(MachineOperand dst, MachineOperand src)
if (src.Width.Size < dst.Width.Size)
r = (TWord) (sbyte) r;
var mask = masks[dst.Width.Size];
TWord sum = (l + r) & mask.value;
TWord sum = l + r & mask.value;
Write(dst, sum);
uint ov = ((~(l ^ r) & (l ^ sum)) & mask.hibit) >> 20;
uint ov = (~(l ^ r) & (l ^ sum) & mask.hibit) >> 20;
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
(r > sum ? 1u : 0u) | // Carry
(sum == 0 ? 1u << 6 : 0u) | // Zero
((sum & mask.hibit) != 0 ? Smask : 0u) | // Sign
(ov) // Overflow
ov // Overflow
;
}

private void Rep()
{
var strInstr = dasm.Current;
this.ignoreRep = true;
ignoreRep = true;
var c = ReadRegister(cxReg);
while (c != 0)
{
Execute(strInstr);
--c;
WriteRegister(cxReg, c);
}
this.ignoreRep = false;
ignoreRep = false;
}

// Repeat while Z flag is set.
private void Repe()
{
var strInstr = dasm.Current;
this.ignoreRep = true;
ignoreRep = true;
var c = ReadRegister(cxReg);
while (c != 0)
{
Expand All @@ -438,13 +438,13 @@ private void Repe()
if ((Flags & Zmask) == 0)
break;
}
this.ignoreRep = false;
ignoreRep = false;
}

private void Repne()
{
var strInstr = dasm.Current;
this.ignoreRep = true;
ignoreRep = true;
var c = ReadRegister(cxReg);
while (c != 0)
{
Expand All @@ -456,7 +456,7 @@ private void Repne()
if ((Flags & Zmask) != 0)
break;
}
this.ignoreRep = false;
ignoreRep = false;
}

protected abstract void Ret();
Expand All @@ -470,9 +470,9 @@ private void Rcl(MachineOperand dst, MachineOperand src)
if ((Flags & Cmask) != 0)
l |= 1;
byte sh = (byte) Read(src);
TWord r = (l << sh) | (l >> (dst.Width.BitSize + 1 - sh));
TWord r = l << sh | l >> dst.Width.BitSize + 1 - sh;
var mask = masks[dst.Width.Size];
Write(dst, (r >> 1) & mask.value);
Write(dst, r >> 1 & mask.value);
Flags &= ~(Cmask | Zmask);
Flags |=
((r & ~1) == 0 ? Zmask : 0u) | // Zero
Expand All @@ -483,11 +483,11 @@ private void Rol(MachineOperand dst, MachineOperand src)
{
TWord l = Read(dst);
byte sh = (byte) Read(src);
TWord r = (l << sh) | (l >> (32 - sh));
TWord r = l << sh | l >> 32 - sh;
Write(dst, r);
Flags &= ~(Zmask);
Flags &= ~Zmask;
Flags |=
(r == 0 ? Zmask : 0u); // Zero
r == 0 ? Zmask : 0u; // Zero
}

protected abstract void Lods(X86Instruction instr);
Expand All @@ -502,7 +502,7 @@ private void Sar(MachineOperand dst, MachineOperand src)
long l = (long) Bits.SignExtend(n, dst.Width.BitSize);
byte sh = (byte) Read(src);
var mask = masks[dst.Width.Size];
TWord r = (TWord)((l >> sh) & mask.value);
TWord r = (TWord) (l >> sh & mask.value);
Write(dst, r);
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
Expand All @@ -515,7 +515,7 @@ private void Shl(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
byte sh = (byte) Read(src);
var (value, hibit) = masks[dst.Width.Size];
TWord r = (l << sh) & value;
TWord r = l << sh & value;
Write(dst, r);
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
Expand All @@ -528,11 +528,11 @@ private void Shr(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
byte sh = (byte) Read(src);
var mask = masks[dst.Width.Size];
TWord r = (l >> sh) & mask.value;
TWord r = l >> sh & mask.value;
Write(dst, r);
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
((l >> (sh-1)) & 1) | // Carry
l >> sh - 1 & 1 | // Carry
(r == 0 ? Zmask : 0u) | // Zero
((r & mask.hibit) != 0 ? Smask : 0u); // Sign
}
Expand Down Expand Up @@ -568,17 +568,17 @@ private void Cmp(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
TWord r = Read(src);
if (src.Width.Size < dst.Width.Size)
r = (TWord)(sbyte)r;
r = (TWord) (sbyte) r;
r = ~r + 1u;
var mask = masks[dst.Width.Size];
TWord diff = (l + r) & mask.value;
uint ov = ((~(l ^ r) & (l ^ diff)) & mask.hibit) >> 20;
TWord diff = l + r & mask.value;
uint ov = (~(l ^ r) & (l ^ diff) & mask.hibit) >> 20;
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
(l < diff ? 1u : 0u) | // Carry
(diff == 0 ? Zmask : 0u) | // Zero
((diff & mask.hibit) != 0 ? Smask : 0u) | // Sign
(ov) // Overflow
ov // Overflow
;
}

Expand All @@ -587,18 +587,18 @@ private void Sub(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
TWord r = Read(src);
if (src.Width.Size < dst.Width.Size)
r = (TWord)(sbyte)r;
r = (TWord) (sbyte) r;
r = ~r + 1u; // Two's complement subtraction.
var mask = masks[dst.Width.Size];
TWord diff = (l + r) & mask.value;
TWord diff = l + r & mask.value;
Write(dst, diff);
uint ov = ((~(l ^ r) & (l ^ diff)) & mask.hibit) >> 20;
uint ov = (~(l ^ r) & (l ^ diff) & mask.hibit) >> 20;
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
(l < diff ? 1u : 0u) | // Carry
(diff == 0 ? Zmask : 0u) | // Zero
((diff & mask.hibit) != 0 ? Smask : 0u) | // Sign
(ov) // Overflow
ov // Overflow
;
}

Expand All @@ -607,9 +607,9 @@ private void And(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
TWord r = Read(src);
if (src.Width.Size < dst.Width.Size)
r = (TWord)(sbyte)r;
r = (TWord) (sbyte) r;
var mask = masks[dst.Width.Size];
var and = (l & r) & mask.value;
var and = l & r & mask.value;
Write(dst, and);
Flags &= ~(Cmask | Zmask | Smask | Omask);
Flags |=
Expand All @@ -623,7 +623,7 @@ private void Not(MachineOperand op)
{
TWord v = Read(op);
var mask = masks[op.Width.Size];
var not = (~v) & mask.value;
var not = ~v & mask.value;
Write(op, not);
// Flags are not affected according to Intel docs.
}
Expand All @@ -633,7 +633,7 @@ private void Or(MachineOperand dst, MachineOperand src)
TWord l = Read(dst);
TWord r = Read(src);
if (src.Width.Size < dst.Width.Size)
r = (TWord)(sbyte)r;
r = (TWord) (sbyte) r;
var mask = masks[dst.Width.Size];
var or = (l | r) & mask.value;
Write(dst, or);
Expand All @@ -649,7 +649,7 @@ private void Dec(MachineOperand op)
{
TWord old = Read(op);
var mask = masks[op.Width.Size];
TWord gnu = (old - 1) & mask.value;
TWord gnu = old - 1 & mask.value;
Write(op, gnu);
uint ov = ((old ^ gnu) & ~gnu & mask.hibit) >> 20;
Flags &= ~(Zmask | Smask | Omask);
Expand All @@ -663,7 +663,7 @@ private void Inc(MachineOperand op)
{
TWord old = Read(op);
var mask = masks[op.Width.Size];
TWord gnu = (old + 1) & mask.value;
TWord gnu = old + 1 & mask.value;
Write(op, gnu);
uint ov = ((old ^ gnu) & gnu & mask.hibit) >> 20;
Flags &= ~(Zmask | Smask | Omask);
Expand Down Expand Up @@ -699,15 +699,15 @@ public void Popa()
public void Pusha()
{
var dt = PrimitiveType.Word32;
var temp = (uint)Registers[X86.Registers.esp.Number];
Push((uint)Registers[X86.Registers.eax.Number], dt);
Push((uint)Registers[X86.Registers.ecx.Number], dt);
Push((uint)Registers[X86.Registers.edx.Number], dt);
Push((uint)Registers[X86.Registers.ebx.Number], dt);
var temp = (uint) Registers[X86.Registers.esp.Number];
Push((uint) Registers[X86.Registers.eax.Number], dt);
Push((uint) Registers[X86.Registers.ecx.Number], dt);
Push((uint) Registers[X86.Registers.edx.Number], dt);
Push((uint) Registers[X86.Registers.ebx.Number], dt);
Push(temp, dt);
Push((uint)Registers[X86.Registers.ebp.Number], dt);
Push((uint)Registers[X86.Registers.esi.Number], dt);
Push((uint)Registers[X86.Registers.edi.Number], dt);
Push((uint) Registers[X86.Registers.ebp.Number], dt);
Push((uint) Registers[X86.Registers.esi.Number], dt);
Push((uint) Registers[X86.Registers.edi.Number], dt);
}

protected abstract TWord Pop(DataType dt);
Expand Down Expand Up @@ -737,7 +737,7 @@ private void Test(MachineOperand op1, MachineOperand op2)
if (op2.Width.Size < op1.Width.Size)
r = (TWord) (sbyte) r;
var mask = masks[op1.Width.Size];
var test = (l & r) & mask.value;
var test = l & r & mask.value;
Flags &= ~(Cmask | Zmask | Smask | Omask); //$TODO: parity.
Flags |=
0 | // Clear carry
Expand Down
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