Merge pull request riscv#217 from ved-rivos/Frozen1

Update to Frozen state

src/cfi_forward.adoc

@@ -617,12 +617,12 @@ at the privilege level the hart was previously in, and the `ELP` is set to
 value `y`, then `ELP` is set to the value of `pelp` if `__y__LPE` is 1;
 otherwise, it is set to `NO_LP_EXPECTED`.
 
-When the Smrnmi extension is implemented, a `MNPELP` field (bit 9) is provided
-in the `mnstatus` CSR to hold the previous `ELP` state on a trap to the RNMI
-handler. When a RNMI trap is delivered, the `MNPELP` is set to `ELP` and `ELP`
-set to `NO_LP_EXPECTED`. Upon a `MNRET`, if the `mnstatus.MNPP` holds the value
-`y`, then `ELP` is set to the value of `MNPELP` if `yLPE` is 1; otherwise, it is
-set to `NO_LP_EXPECTED`.
+When the Smrnmi cite:[SMRNMI] extension is implemented, a `MNPELP` field (bit 9)
+is provided in the `mnstatus` CSR to hold the previous `ELP` state on a trap to
+the RNMI handler. When a RNMI trap is delivered, the `MNPELP` is set to `ELP`
+and `ELP` set to `NO_LP_EXPECTED`. Upon a `MNRET`, if the `mnstatus.MNPP` holds
+the value `y`, then `ELP` is set to the value of `MNPELP` if `yLPE` is 1;
+otherwise, it is set to `NO_LP_EXPECTED`.
 
 [NOTE]
 ====

src/contributors.adoc

@@ -3,4 +3,4 @@
 This RISC-V specification has been contributed to directly or indirectly by (in alphabetical order):
 
 [%hardbreaks]
-Adam Zabrocki, Andrew Waterman, Antoine Linarès, Argyro Palli, Dean Liberty, Deepak Gupta, Eckhard Delfs, George Christou, Greg Favor, Greg McGary, Henry Hsieh, Johan Klockars, John Hauser, John Ingalls, Kip Walker, Kito Cheng, Lasse Collin, Liu Zhiwei, Mark Hill, Nick Kossifidis, Phillip Reames, Rui Ueyama, Sami Tolvanen, Sotiris Ioannidis, Stefan O'Rear, Thurston Dang, Tsukasa OI, Vedvyas Shanbhogue,
+Adam Zabrocki, Andrew Waterman, Antoine Linarès, Argyro Palli, Dean Liberty, Deepak Gupta, Eckhard Delfs, George Christou, Greg Favor, Greg McGary, Henry Hsieh, Johan Klockars, John Hauser, John Ingalls, Kip Walker, Kito Cheng, Lasse Collin, Liu Zhiwei, Mark Hill, Nick Kossifidis, Phillip Reames, Rui Ueyama, Sami Tolvanen, Sotiris Ioannidis, Stefan O'Rear, Thurston Dang, Tsukasa OI, Vedvyas Shanbhogue

src/riscv-cfi.adoc

@@ -1,21 +1,19 @@
 = RISC-V Shadow Stacks and Landing Pads
 :description: RISC-V Shadow-stack and Landing-pads Task Group
 :company: RISC-V.org
-:revdate: 07/2023
-:revnumber: 0.1
-:revremark: This document is in development. Assume everything can change. See http://riscv.org/spec-state for details.
+:revdate: 03/2024
+:revnumber: 1.0
+:revremark: This document is in Frozen. See http://riscv.org/spec-state for details.
 :url-riscv: http://riscv.org
 :doctype: book
 :preface-title: Preamble
 :colophon:
 :appendix-caption: Appendix
-// https://docs.asciidoctor.org/asciidoc/latest/macros/images-directory/
 :imagesdir: ../docs-resources/images
 :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
 // Settings:
 :experimental:
 :reproducible:
-//:WaveDromEditorApp: app/wavedrom-editor.app
 :imagesoutdir: build/images
 :srcdir: src
 :bibtex-file: {srcdir}/sslpcfi.bib
@@ -38,11 +36,12 @@ endif::[]
 :xrefstyle: short
 
 [WARNING]
-.This document is in the link:http://riscv.org/spec-state[Development state]
+.This document is in the link:http://riscv.org/spec-state[Frozen state]
 ====
-Assume everything can change. This draft specification will change before
-being accepted as standard, so implementations made to this draft
-specification will likely not conform to the future standard.
+Change is extremely unlikely. A high threshold will be used, and a change will
+only occur because of some truly critical issue being identified during the
+public review cycle. Any other desired or needed changes can be the subject of a
+follow-on new extension.
 ====
 
 [preface]
@@ -53,13 +52,11 @@ Attribution 4.0 International License (CC-BY 4.0). The full
 license text is available at
 https://creativecommons.org/licenses/by/4.0/.
 
-Copyright 2022 by RISC-V International.
+Copyright 2022 - 2024 by RISC-V International.
 
 [preface]
 include::contributors.adoc[]
-
 include::cfi_intro.adoc[]
 include::cfi_backward.adoc[]
 include::cfi_forward.adoc[]
-//the index must precede the bibliography
 include::cfi_biblio.adoc[]

src/sslpcfi.bib

@@ -1,18 +1,23 @@
 @electronic{UNPRIV,
-  title = {RISC-V Instruction Set Manual, Volume I: Unprivileged ISA },
+  title = {RISC-V Instruction Set Manual, Volume I: Unprivileged ISA},
   url = {https://github.com/riscv/riscv-isa-manual},
   year = {}
 }
 @electronic{PRIV,
-  title = {RISC-V Instruction Set Manual, Volume II: Privileged Architecture },
+  title = {RISC-V Instruction Set Manual, Volume II: Privileged Architecture},
   url = {https://github.com/riscv/riscv-isa-manual},
   year = {}
 }
 @electronic{ZIMOP,
-  title = {"Zimop" May-Be-Operations Extension},
+  title = {Zimop May-Be-Operations Extension},
   url = {https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc},
   year = {}
 }
+@electronic{SMRNMI,
+  title = {Smrnmi Standard Extension for Resumable Non-Maskable Interrupts},
+  url = {https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc},
+  year = {}
+}
 @electronic{ASM-MANUAL,
   title = {RISC-V Assembly Programmer's Manual},
   url = {https://github.com/riscv-non-isa/riscv-asm-manual},