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Intel LA57 Support #6

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Champ-Goblem opened this issue Apr 8, 2024 · 2 comments
Open

Intel LA57 Support #6

Champ-Goblem opened this issue Apr 8, 2024 · 2 comments
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@bysui
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enhancement New feature or request

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@Champ-Goblem
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We are attempting to test out PVM on GCP through their newer machine types (N4/C3) however when trying to load the PVM kernel module we see the following error in the kernel logs:

[  152.852592] kvm_pvm: Supporting for LA57 host is not fully implemented yet.

We managed to avoid this error by disabling 5-level paging support when compiling the kernel (CONFIG_X86_5LEVEL=n), however, it would be good to know if support for this will be added at some point, and ideally to have this as a way to track that support.

Thanks
@laijs
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laijs commented Apr 9, 2024

@Champ-Goblem Thanks for report, we are adding the support of it. We will report the progresses here as possible as we can.

@bysui bysui added the enhancement New feature or request label Apr 9, 2024
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
x86/mm: Reserve a range in the 5-level page tables for PVM guest
7497a07 
For a 4-level paging mode PVM guest, only the top 128TB is canonical.
When KASLR is enabled for 5-level page tables, this range overlaps with
the KASLR entropy range. Therefore, set the end address to -128TB to
reserve a range for the PVM guest. Regarding the KASAN area, the size is
sufficient.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
KVM: x86/mmu: Clear 'role.host_mmu_la57_top_p4d' when calculating chi…
5ceb9c5 
…ld SP role

The 'role.host_mmu_la57_top_p4d' bit is only allowed for L4 SP and
should not be inherited when calculating the child SP role. Otherwise,
wrong spte will be set in drop_parent_pte() and it will result in a
broken SPT.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
KVM: x86/PVM: Add support for 5-level paging mode
7405002 
When 5-level paging mode is enabled on the host, the guest can be either
in 4-level paging mode or 5-level paging mode. For 4-level paging mode,
only the topmost 128TB is canonical. Therefore, the hypervisor needs to
reserve two ranges: one in the vmalloc area for the 5-level paging mode
guest, and another in the topmost 128TB for the 4-level paging mode
guest. If the allocation of the range for the 5-level paging mode guest
fails, then 5-level paging mode is disabled for the guest.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
x86/pvm: Add missing flags in pvm_write_cr3() when guest is in 5-leve…
6a222e7 
…l paging mode

According to the PVM specification, a flag in the PVM_HC_LOAD_PGTBL
hypercall is allowed to directly change the paging mode. Therefore, add
the missing flags when the guest is in 5-level paging mode. This
preparation is done to support 5-level paging mode guests.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
x86/pvm: Add support for 5-level paging mode guest
48eb9d3 
Similar to the 4-level paging mode guest, the 5-level paging mode guest
should lie within the allowed range provided by the hypervisor.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
bysui added a commit that referenced this issue Apr 25, 2024
@bysui
x86/boot: Support for compressed kernel booting
858242d 
The 5-level paging mode is enabled in compressed kernel booting and it
uses the CPUID instruction to detect 5-level paging support. For PVM
guest, pvm_cpuid() should be used instead of the CPUID instruction, so
detect PVM hypervisor support early in configure_5level_paging().
Additionally, relocation for PVM guest during booting should be avoided.
This is because there is only the first 4G identity mapping, and if
physical address randomization is enabled, a #PF exception will occur if
the chosen output address is over the first 4G range. Therefore, for
simplification, physical address randomization should be avoided. As for
virtual address randomization, it should occur after entering the kernel
entry.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Link: #6
@bysui bysui self-assigned this Apr 25, 2024
@bysui
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bysui commented Apr 25, 2024 •
edited
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Hi @Champ-Goblem , We have provided basic support for 5-level paging mode hosts and 5-level paging mode guests. I have tested booting 4-level paging mode guests and 5-level paging mode guests on a 5-level paging mode host, but it's not fully tested, as we don't have CI/CD now. Please note that migrating a 4-level paging mode guest from a 5-level paging mode host to 4-level paging mode host is currently not successful.

If any problems occur, please feel free to report them. Thanks!

pojntfx added a commit to loopholelabs/linux-pvm-ci that referenced this issue Apr 26, 2024
@pojntfx
refactor: Enable 5-level paging on GCP since (see virt-pvm/linux#6 (c…
cdaee13 
…omment))
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@laijs @bysui @Champ-Goblem