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@xiangze-arm xiangze-arm commented Oct 21, 2025

Description

  • Add oneDNN/ACL matmul path for AArch64 in fused moe

Test Plan

  • Tested locally with Qwen3-30B-A3B model.
  • Unit test pytest tests/kernels/moe/test_moe.py -k test_cpu_fused_moe_basic

Test Result

  • End to end test result is ok.
  • Unit test passes.

Performance

With this PR, MoE can go into onednn_mm path on AArch64 CPU. On 32 Neoverse-N2 cores, this PR gets about 1.6x throughput compared with current default path.

Bench command:

vllm bench throughput --dtype=bfloat16 --num-prompts 64 --seed 0 --dataset-name sharegpt --max-model-len=2048 --input_len=64 --model Qwen3-30B-A3B

- Add oneDNN/ACL matmul path for AArch64
- Use silu_and_mul Op

Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>
@xiangze-arm xiangze-arm requested a review from mgoin as a code owner October 21, 2025 03:47
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Code Review

This pull request improves CPU performance for fused MoE layers by introducing a oneDNN/ACL matmul path for AArch64 architectures and leveraging a custom silu_and_mul operator. The changes are well-implemented, preparing oneDNN matmul handlers during initialization and using them in the forward pass. While this is a solid performance enhancement, I've identified a high-severity issue concerning model serialization. The created oneDNN handlers are not serializable, and attaching them to the model can lead to crashes upon saving and reloading the model.

Comment on lines +256 to +267
gate_up_handle = ops.create_onednn_mm(layer_w13_weight.t(), 32)
layer.gate_up_linear.append(
lambda x, handle=gate_up_handle, bias=layer_w13_bias: ops.onednn_mm(
handle, x, bias
)
)
down_handle = ops.create_onednn_mm(layer_w2_weight.t(), 32)
layer.down_linear.append(
lambda x, handle=down_handle, bias=layer_w2_bias: ops.onednn_mm(
handle, x, bias
)
)
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high

The CPUDNNLGEMMHandler objects created by ops.create_onednn_mm contain pointers to C++ state and are not serializable. Storing lambdas that capture these handlers in layer.gate_up_linear and layer.down_linear will cause issues if the model is serialized (e.g., with pickle or torch.save). Upon deserialization, the handler pointers will be invalid, which can lead to segmentation faults when the model is used or garbage collected.

To prevent this, the CPUDNNLGEMMHandler class should be made non-picklable by implementing __getstate__ to raise an exception. Since that class is not in this file, an alternative is to avoid storing these handlers on the torch.nn.Module instance if model serialization is a possibility. If serialization is not a supported use case for CPU-based models, this might be acceptable, but it's a significant risk.

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Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>
@xiangze-arm
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I saw vllm crash when running unit test locally with pytest tests/kernels/moe/test_moe.py -k test_cpu_fused_moe_basic

It seems the issue is not directly related with this PR. But the moe test exposed an issue in onednn MatMul cache.

The issue: ClassMatmulCacheKey in MatMulPrimitiveHandler does not consider different data type. Two onednn_mm with same weight size but different data types wrongly share the same cache key. moe test tests bf16 and fp32 with the same weight size, causes crash.

The tests passed when I tested bf16 and fp32 separately.

@xiangze-arm
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@mgoin @bigPYJ1151 Can you help to review this PR?

cc @fadara01 @nikhil-arm

@fadara01
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Hi @xiangze-arm - can you test again with #27472?

@xiangze-arm
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I have tested this PR with #27472 fix. The unit test passed without crash.

PR description is also updated with performance result (1.6x throughput improvement).

@fadara01
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@bigPYJ1151 could you have a look at this please?

Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>
@xiangze-arm
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I benchmarked the performance impact of silu_and_mul change, and it is small(~ 3% overall improvement). So I have removed silu_and_mul change due to concerns.

This PR only contains the feature of adding new oneDNN/ACL path in cpu fused moe now.

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fadara01 commented Nov 3, 2025

Thank you, I wasn't really asking for it to be removed, just for more insights about why we chose to use it.
We'll integrate it once we improve the Arm vectorizer in vllm

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fadara01 commented Nov 3, 2025

@bigPYJ1151 could you please help review this change?

@bigPYJ1151 bigPYJ1151 enabled auto-merge (squash) November 3, 2025 09:47
@github-actions github-actions bot added the ready ONLY add when PR is ready to merge/full CI is needed label Nov 3, 2025
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fadara01 commented Nov 4, 2025

Ah, those CI failures are unrelated.
@xiangze-arm can you try updating your branch s.t. we can get this merged?

@bigPYJ1151 bigPYJ1151 merged commit c757a15 into vllm-project:main Nov 6, 2025
50 checks passed
ZhengHongming888 pushed a commit to ZhengHongming888/vllm that referenced this pull request Nov 8, 2025
Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>
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4 participants