Merge with upstream (#239)

wasmfx · Oct 16, 2024 · 522ded7 · 522ded7
2 parents dc2f2f1 + ab093a3
commit 522ded7
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diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -781,7 +781,7 @@ jobs:
  - uses: ./.github/actions/install-rust
 
  # Install OpenVINO
- - uses: abrown/install-openvino-action@v8
+ - uses: abrown/install-openvino-action@v9
  if: runner.arch == 'X64'
 
  # Install WinML for testing wasi-nn WinML backend. WinML is only available

diff --git a/Cargo.lock b/Cargo.lock
diff --git a/cranelift/codegen/meta/src/isa/x86.rs b/cranelift/codegen/meta/src/isa/x86.rs
@@ -17,6 +17,12 @@ pub(crate) fn define() -> TargetIsa {
  "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]",
  false,
  );
+ let has_cmpxchg16b = settings.add_bool(
+ "has_cmpxchg16b",
+ "Has support for CMPXCHG16b.",
+ "CMPXCHG16b: CPUID.01H:ECX.CMPXCHG16B[bit 13]",
+ false,
+ );
  let has_sse41 = settings.add_bool(
  "has_sse41",
  "Has support for SSE4.1.",
@@ -106,6 +112,7 @@ pub(crate) fn define() -> TargetIsa {
  false,
  );
 
+ settings.add_predicate("use_cmpxchg16b", predicate!(has_cmpxchg16b));
  settings.add_predicate("use_ssse3", predicate!(has_ssse3));
  settings.add_predicate("use_sse41", predicate!(has_sse41));
  settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
@@ -141,14 +148,30 @@ pub(crate) fn define() -> TargetIsa {
  // Intel CPUs
 
  // Netburst
- settings.add_preset("nocona", "Nocona microarchitecture.", preset!(sse3));
+ settings.add_preset(
+ "nocona",
+ "Nocona microarchitecture.",
+ preset!(sse3 && has_cmpxchg16b),
+ );
 
  // Intel Core 2 Solo/Duo
- settings.add_preset("core2", "Core 2 microarchitecture.", preset!(sse3));
- settings.add_preset("penryn", "Penryn microarchitecture.", preset!(sse41));
+ settings.add_preset(
+ "core2",
+ "Core 2 microarchitecture.",
+ preset!(sse3 && has_cmpxchg16b),
+ );
+ settings.add_preset(
+ "penryn",
+ "Penryn microarchitecture.",
+ preset!(sse41 && has_cmpxchg16b),
+ );
 
  // Intel Atom CPUs
- let atom = settings.add_preset("atom", "Atom microarchitecture.", preset!(ssse3));
+ let atom = settings.add_preset(
+ "atom",
+ "Atom microarchitecture.",
+ preset!(ssse3 && has_cmpxchg16b),
+ );
  settings.add_preset("bonnell", "Bonnell microarchitecture.", preset!(atom));
  let silvermont = settings.add_preset(
  "silvermont",
@@ -186,7 +209,7 @@ pub(crate) fn define() -> TargetIsa {
  let nehalem = settings.add_preset(
  "nehalem",
  "Nehalem microarchitecture.",
- preset!(sse42 && has_popcnt),
+ preset!(sse42 && has_popcnt && has_cmpxchg16b),
  );
  settings.add_preset("corei7", "Core i7 microarchitecture.", preset!(nehalem));
  let westmere = settings.add_preset("westmere", "Westmere microarchitecture.", preset!(nehalem));
@@ -229,7 +252,15 @@ pub(crate) fn define() -> TargetIsa {
  let knights_landing = settings.add_preset(
  "knl",
  "Knights Landing microarchitecture.",
- preset!(has_popcnt && has_avx512f && has_fma && has_bmi1 && has_bmi2 && has_lzcnt),
+ preset!(
+ has_popcnt
+ && has_avx512f
+ && has_fma
+ && has_bmi1
+ && has_bmi2
+ && has_lzcnt
+ && has_cmpxchg16b
+ ),
  );
  settings.add_preset(
  "knm",
@@ -312,22 +343,22 @@ pub(crate) fn define() -> TargetIsa {
  settings.add_preset(
  "opteron-sse3",
  "Opteron microarchitecture with support for SSE3 instructions.",
- preset!(sse3),
+ preset!(sse3 && has_cmpxchg16b),
  );
  settings.add_preset(
  "k8-sse3",
  "K8 Hammer microarchitecture with support for SSE3 instructions.",
- preset!(sse3),
+ preset!(sse3 && has_cmpxchg16b),
  );
  settings.add_preset(
  "athlon64-sse3",
  "Athlon 64 microarchitecture with support for SSE3 instructions.",
- preset!(sse3),
+ preset!(sse3 && has_cmpxchg16b),
  );
  let barcelona = settings.add_preset(
  "barcelona",
  "Barcelona microarchitecture.",
- preset!(has_popcnt && has_lzcnt),
+ preset!(has_popcnt && has_lzcnt && has_cmpxchg16b),
  );
  settings.add_preset(
  "amdfam10",
@@ -338,7 +369,7 @@ pub(crate) fn define() -> TargetIsa {
  let btver1 = settings.add_preset(
  "btver1",
  "Bobcat microarchitecture.",
- preset!(ssse3 && has_lzcnt && has_popcnt),
+ preset!(ssse3 && has_lzcnt && has_popcnt && has_cmpxchg16b),
  );
  settings.add_preset(
  "btver2",
@@ -349,7 +380,7 @@ pub(crate) fn define() -> TargetIsa {
  let bdver1 = settings.add_preset(
  "bdver1",
  "Bulldozer microarchitecture",
- preset!(has_lzcnt && has_popcnt && ssse3),
+ preset!(has_lzcnt && has_popcnt && ssse3 && has_cmpxchg16b),
  );
  let bdver2 = settings.add_preset(
  "bdver2",
@@ -366,7 +397,9 @@ pub(crate) fn define() -> TargetIsa {
  let znver1 = settings.add_preset(
  "znver1",
  "Zen (first generation) microarchitecture.",
- preset!(sse42 && has_popcnt && has_bmi1 && has_bmi2 && has_lzcnt && has_fma),
+ preset!(
+ sse42 && has_popcnt && has_bmi1 && has_bmi2 && has_lzcnt && has_fma && has_cmpxchg16b
+ ),
  );
  let znver2 = settings.add_preset(
  "znver2",
@@ -397,7 +430,7 @@ pub(crate) fn define() -> TargetIsa {
  let x86_64_v2 = settings.add_preset(
  "x86-64-v2",
  "Generic x86-64 (V2) microarchitecture.",
- preset!(sse42 && has_popcnt),
+ preset!(sse42 && has_popcnt && has_cmpxchg16b),
  );
  let x86_64_v3 = settings.add_preset(
  "x84_64_v3",