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DudeplayzDudeplayz
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style(instruction.spec): add comments for missing instruction tests and reorder tests according to the AVR datasheet
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‎src/cpu/instruction.spec.ts‎

Lines changed: 103 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,10 @@ describe('avrInstruction', () => {
115115
expect(cpu.data[SREG]).toEqual(SREG_H | SREG_Z | SREG_C);
116116
});
117117

118+
/**
119+
* ADIW, AND, ANDI, ASR
120+
*/
121+
118122
it('should execute `BCLR 2` instruction', () => {
119123
loadProgram('BCLR 2');
120124
cpu.data[SREG] = 0xff;
@@ -176,14 +180,10 @@ describe('avrInstruction', () => {
176180
expect(cpu.cycles).toEqual(1);
177181
});
178182

179-
it('should execute `CBI 0x0c, 5`', () => {
180-
loadProgram('CBI 0x0c, 5');
181-
cpu.data[0x2c] = 0b11111111;
182-
avrInstruction(cpu);
183-
expect(cpu.pc).toEqual(1);
184-
expect(cpu.cycles).toEqual(1);
185-
expect(cpu.data[0x2c]).toEqual(0b11011111);
186-
});
183+
/**
184+
* BRCC, BRCS, BREAK, BREQ, BRGE, BRHC, BRHS, BRID, BRIE, BRLO,
185+
* BRLT, BRMI, BRNE, BRPL, BRSH, BRTC, BRTS, BRVC, BRVS, BSET, BST
186+
*/
187187

188188
it('should execute `CALL` instruction', () => {
189189
loadProgram('CALL 0xb8');
@@ -208,6 +208,19 @@ describe('avrInstruction', () => {
208208
expect(cpu.data[SP]).toEqual(147); // SP should be decremented by 3
209209
});
210210

211+
it('should execute `CBI 0x0c, 5`', () => {
212+
loadProgram('CBI 0x0c, 5');
213+
cpu.data[0x2c] = 0b11111111;
214+
avrInstruction(cpu);
215+
expect(cpu.pc).toEqual(1);
216+
expect(cpu.cycles).toEqual(1);
217+
expect(cpu.data[0x2c]).toEqual(0b11011111);
218+
});
219+
220+
/**
221+
* CBR, CLC, CLH, CLI, CLN, CLR, CLS, CLT, CLV, CLZ, COM, CP
222+
*/
223+
211224
it('should execute `CPC r27, r18` instruction', () => {
212225
loadProgram('CPC r27, r18');
213226
cpu.data[r18] = 0x1;
@@ -265,6 +278,10 @@ describe('avrInstruction', () => {
265278
expect(cpu.cycles).toEqual(3);
266279
});
267280

281+
/**
282+
* DEC, DES
283+
*/
284+
268285
it('should execute `EICALL` instruction', () => {
269286
cpu = new CPU(new Uint16Array(0x20000));
270287
loadProgram('EICALL');
@@ -336,6 +353,10 @@ describe('avrInstruction', () => {
336353
expect(cpu.data[RAMPZ]).toEqual(0x0); // verify that RAMPZ was reset to zero
337354
});
338355

356+
/**
357+
* EOR, FMUL, FMULS, FMULSU
358+
*/
359+
339360
it('should execute `ICALL` instruction', () => {
340361
loadProgram('ICALL');
341362
cpu.data[SPH] = 0;
@@ -444,23 +465,6 @@ describe('avrInstruction', () => {
444465
expect(cpu.data[0x80]).toEqual(0x55);
445466
});
446467

447-
it('should execute `LDI r28, 0xff` instruction', () => {
448-
loadProgram('LDI r28, 0xff');
449-
avrInstruction(cpu);
450-
expect(cpu.pc).toEqual(0x1);
451-
expect(cpu.cycles).toEqual(1);
452-
expect(cpu.data[Y]).toEqual(0xff);
453-
});
454-
455-
it('should execute `LDS r5, 0x150` instruction', () => {
456-
loadProgram('LDS r5, 0x150');
457-
cpu.data[0x150] = 0x7a;
458-
avrInstruction(cpu);
459-
expect(cpu.pc).toEqual(0x2);
460-
expect(cpu.cycles).toEqual(2);
461-
expect(cpu.data[r5]).toEqual(0x7a);
462-
});
463-
464468
it('should execute `LD r1, X` instruction', () => {
465469
loadProgram('LD r1, X');
466470
cpu.data[0xc0] = 0x15;
@@ -582,6 +586,27 @@ describe('avrInstruction', () => {
582586
expect(cpu.data[Z]).toEqual(0x80); // verify that Z was unchanged
583587
});
584588

589+
it('should execute `LDI r28, 0xff` instruction', () => {
590+
loadProgram('LDI r28, 0xff');
591+
avrInstruction(cpu);
592+
expect(cpu.pc).toEqual(0x1);
593+
expect(cpu.cycles).toEqual(1);
594+
expect(cpu.data[Y]).toEqual(0xff);
595+
});
596+
597+
it('should execute `LDS r5, 0x150` instruction', () => {
598+
loadProgram('LDS r5, 0x150');
599+
cpu.data[0x150] = 0x7a;
600+
avrInstruction(cpu);
601+
expect(cpu.pc).toEqual(0x2);
602+
expect(cpu.cycles).toEqual(2);
603+
expect(cpu.data[r5]).toEqual(0x7a);
604+
});
605+
606+
/**
607+
* LDS (16-bit)
608+
*/
609+
585610
it('should execute `LPM` instruction', () => {
586611
loadProgram('LPM');
587612
cpu.progMem[0x40] = 0xa0;
@@ -615,6 +640,10 @@ describe('avrInstruction', () => {
615640
expect(cpu.data[Z]).toEqual(0x81); // verify that Z was incremented
616641
});
617642

643+
/**
644+
* LSL
645+
*/
646+
618647
it('should execute `LSR r7` instruction', () => {
619648
loadProgram('LSR r7');
620649
cpu.data[r7] = 0x45;
@@ -717,6 +746,10 @@ describe('avrInstruction', () => {
717746
expect(cpu.cycles).toEqual(1);
718747
});
719748

749+
/**
750+
* OR, ORI
751+
*/
752+
720753
it('should execute `OUT 0x3f, r1` instruction', () => {
721754
loadProgram('OUT 0x3f, r1');
722755
cpu.data[r1] = 0x5a;
@@ -843,6 +876,10 @@ describe('avrInstruction', () => {
843876
expect(cpu.cycles).toEqual(2);
844877
});
845878

879+
/**
880+
* ROL
881+
*/
882+
846883
it('should execute `ROR r0` instruction', () => {
847884
loadProgram('ROR r0');
848885
cpu.data[r0] = 0x11;
@@ -853,6 +890,18 @@ describe('avrInstruction', () => {
853890
expect(cpu.data[SREG]).toEqual(SREG_S | SREG_V | SREG_C);
854891
});
855892

893+
it('should execute `SBC r0, r1` instruction when carry is on and result overflows', () => {
894+
loadProgram('SBC r0, r1');
895+
cpu.data[r0] = 0;
896+
cpu.data[r1] = 10;
897+
cpu.data[95] = SREG_C;
898+
avrInstruction(cpu);
899+
expect(cpu.pc).toEqual(1);
900+
expect(cpu.cycles).toEqual(1);
901+
expect(cpu.data[r0]).toEqual(245);
902+
expect(cpu.data[SREG]).toEqual(SREG_H | SREG_S | SREG_N | SREG_C);
903+
});
904+
856905
it('should execute `SBCI r23, 3`', () => {
857906
loadProgram('SBCI r23, 3');
858907
cpu.data[r23] = 3;
@@ -872,6 +921,10 @@ describe('avrInstruction', () => {
872921
expect(cpu.data[0x2c]).toEqual(0b00101111);
873922
});
874923

924+
/**
925+
* SBIC
926+
*/
927+
875928
it('should execute `SBIS 0x0c, 5` when bit is clear', () => {
876929
loadProgram('SBIS 0x0c, 5');
877930
cpu.data[0x2c] = 0b00001111;
@@ -896,14 +949,10 @@ describe('avrInstruction', () => {
896949
expect(cpu.cycles).toEqual(3);
897950
});
898951

899-
it('should execute `STS 0x151, r31` instruction', () => {
900-
loadProgram('STS 0x151, r31');
901-
cpu.data[r31] = 0x80;
902-
avrInstruction(cpu);
903-
expect(cpu.pc).toEqual(2);
904-
expect(cpu.cycles).toEqual(2);
905-
expect(cpu.data[0x151]).toEqual(0x80);
906-
});
952+
/**
953+
* SBIW, SBR, SBRC, SBRS, SEC, SEH, SEI, SEN, SER, SES, SET, SEV, SEZ,
954+
* SLEEP, SPM, SPM #2
955+
*/
907956

908957
it('should execute `ST X, r1` instruction', () => {
909958
loadProgram('ST X, r1');
@@ -1026,6 +1075,19 @@ describe('avrInstruction', () => {
10261075
expect(cpu.data[Z]).toEqual(0x50); // verify that Z was unchanged
10271076
});
10281077

1078+
it('should execute `STS 0x151, r31` instruction', () => {
1079+
loadProgram('STS 0x151, r31');
1080+
cpu.data[r31] = 0x80;
1081+
avrInstruction(cpu);
1082+
expect(cpu.pc).toEqual(2);
1083+
expect(cpu.cycles).toEqual(2);
1084+
expect(cpu.data[0x151]).toEqual(0x80);
1085+
});
1086+
1087+
/**
1088+
* STS (16-bit)
1089+
*/
1090+
10291091
it('should execute `SUB r0, r1` instruction when result overflows', () => {
10301092
loadProgram('SUB r0, r1');
10311093
cpu.data[r0] = 0;
@@ -1037,6 +1099,10 @@ describe('avrInstruction', () => {
10371099
expect(cpu.data[SREG]).toEqual(SREG_S | SREG_N | SREG_C);
10381100
});
10391101

1102+
/**
1103+
* SUBI
1104+
*/
1105+
10401106
it('should execute `SWAP r1` instruction', () => {
10411107
loadProgram('SWAP r1');
10421108
cpu.data[r1] = 0xa5;
@@ -1046,6 +1112,10 @@ describe('avrInstruction', () => {
10461112
expect(cpu.data[r1]).toEqual(0x5a);
10471113
});
10481114

1115+
/**
1116+
* TST
1117+
*/
1118+
10491119
it('should execute `WDR` instruction and call `cpu.onWatchdogReset`', () => {
10501120
loadProgram('WDR');
10511121
cpu.onWatchdogReset = jest.fn();

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