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pip prod(deps): bump riscemu from 2.1.1 to 2.2.7 #3

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@dependabot dependabot bot commented on behalf of github Aug 19, 2024

Bumps riscemu from 2.1.1 to 2.2.7.

Release notes

Sourced from riscemu's releases.

v2.2.7 - Bigger Better Bugfixes

New in v2.2.7

  • BugFix: Fix malloc implementation from being just wrong to being right (I think?)
  • BugFix: Fix MMU.translate_address to actually return the best match (wow!)
  • Feature: The instruction trace now contains register and symbol values starting at verbosity level 3
  • BugFix: RVDebug got better at finding out if a float or int register was meant

Thanks @​superlopuh for pointing out all these shortcomings, happy I got them fixed for you!

Full Changelog: AntonLydike/riscemu@v2.2.6...v2.2.7

v2.2.6 - Incremental Improvements (attempt 2)

What's Changed

  • Feature: Canonicalize register names when parsing, converting e.g. x0 -> zero or fp -> s0.
  • Feature: Added support for fcvt.d.w[u] and fcvt.w[u].d instructions
  • BugFix: Fixed that registers were treated as UInt32s instead of Int32 (this may have caused subtle bugs before)
  • Feature: Added the remainder of the M extension
  • BugFix: Fixed a bug in the overflow behavior of mulh
  • BugFix: Fix faulty length assertion in jalr

(You can also read the Changelog.md file in this release)

New Contributors

Full Changelog: AntonLydike/riscemu@v2.2.5...v2.2.6

v2.2.5 - Emergency Release

2.2.5

  • BugFix: Fix missed import in core.simple_instruction

Full Changelog: AntonLydike/riscemu@v2.2.4...v2.2.5

v2.2.4 - Snitch support is getting better

What's Changed

  • BugFix: Found and added some missing floating point registers (ft8 to ft11)
  • Feature: Add frep support to the snitch emulation
  • Feature: Add support for 64-bit floats to the snitch Xssr emulation

Full Changelog: AntonLydike/riscemu@v2.2.3...v2.2.4

v2.2.3 - Flen=64 support and some bugfixes

What's Changed

  • Feature: Adding support for 64 bit floating point operations

... (truncated)

Changelog

Sourced from riscemu's changelog.

2.2.7

  • BugFix: Fix malloc implementation from being just wrong to being right (I think?)
  • BugFix: Fix MMU.translate_address to actually return the best match (wow!)
  • Feature: The instruction trace now contains register and symbol values starting at verbosity level 3
  • BugFix: RVDebug got better at finding out if a float or int register was meant

2.2.6

  • Feature: Canonicalize register names when parsing, converting e.g. x0 -> zero or fp -> s0.
  • Feature: Added support for fcvt.d.w[u] and fcvt.w[u].d instructions
  • BugFix: Fixed that registers were treated as UInt32s instead of Int32 (this may have caused subtle bugs before)
  • Feature: Added the remainder of the M extension
  • BugFix: Fixed a bug in the overflow behavior of mulh
  • BugFix: Fix faulty length assertion in jalr

2.2.5

  • BugFix: Fix missed import in core.simple_instruction

2.2.4

  • BugFix: Found and added some missing floating point registers (ft8 to ft11)
  • Feature: Add frep support to the snitch emulation
  • Feature: Add support for 64-bit floats to the snitch Xssr emulation

2.2.3

  • Feature: Adding support for 64 bit floating point operations
  • BugFix: Fix a bug where -o libc would fail with packaged versions of riscemu
  • BugFix: Fix __all__ to now properly work (use name strings instead of values)

2.2.2

  • Dev: Add __all__ to riscemu.{core,instructions,decoder} modules to make pyright in other projects happy
  • Perf: very minor fix related to not converting values twice when loaded from memory

2.2.1

Version bump to re-trigger CI run.

2.2.0

  • Feature: Added Zicsr extension and with that support for CSRs
  • Feature: Starting to add support for Snitch architecture (Xssr)
  • Feature: Add support for .p2align assembler directive
  • Rework: Improve handling of immediates, so that beq a0, a1, 1b and beq a0, a1, -16 can both can be handled correctly.
  • BugFix: Fix some more errors in the RV32F implementation
  • Dev: Move to poetry for project development environment
  • Dev: Module refactoring, core datastructures now mostly live inside riscemu.core

... (truncated)

Commits
  • ee704f3 release v2.2.7
  • eaf3cb5 a bunch of fixes
  • c79bc35 release v2.2.6, properly now
  • 18d2ffe release v2.2.6
  • 6281f44 Feature m instruction set (#48)
  • 5e758a2 floats: Add fcvt instructions for doubles, and fix their overflow behaviour t...
  • 5735f9f a bit of cleanup
  • 3ea7637 add PR template
  • 2732213 fix formatting issues, add changelog for previous commit
  • 4184982 Allow register indices in addition to ABI names (#52)
  • Additional commits viewable in compare view

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Bumps [riscemu](https://github.com/antonlydike/riscemu) from 2.1.1 to 2.2.7.
- [Release notes](https://github.com/antonlydike/riscemu/releases)
- [Changelog](https://github.com/AntonLydike/riscemu/blob/master/CHANGELOG.md)
- [Commits](AntonLydike/riscemu@v2.1.1...v2.2.7)

---
updated-dependencies:
- dependency-name: riscemu
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <support@github.com>
@dependabot dependabot bot added the dependencies Pull requests that update a dependency file label Aug 19, 2024
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