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backend: (riscv) Allocate ub and step before loop, and lb after #2619

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merged 2 commits into from
May 28, 2024

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First of two PRs fixing our register allocator, this one allows for reuse of the iteration argument, which is currently never freed.

@superlopuh superlopuh added bug Something isn't working backend Compiler backend in xDSL labels May 21, 2024
@superlopuh superlopuh self-assigned this May 21, 2024
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codecov bot commented May 21, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 89.62%. Comparing base (6252a84) to head (58ff57e).

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #2619   +/-   ##
=======================================
  Coverage   89.62%   89.62%           
=======================================
  Files         358      358           
  Lines       45676    45678    +2     
  Branches     6888     6887    -1     
=======================================
+ Hits        40935    40937    +2     
  Misses       3687     3687           
  Partials     1054     1054           

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@AntonLydike AntonLydike changed the title backend: (riscv) allocate ub and step before loop, and lb after backend: (riscv) Allocate ub and step before loop, and lb after May 22, 2024
@@ -29,18 +29,18 @@ riscv_func.func @main() {
// CHECK-LIVENESS-BLOCK-NAIVE: builtin.module {
// CHECK-LIVENESS-BLOCK-NAIVE-NEXT: riscv_func.func @external() -> ()
// CHECK-LIVENESS-BLOCK-NAIVE-NEXT: riscv_func.func @main() {
// CHECK-LIVENESS-BLOCK-NAIVE-NEXT: %{{.+}} = riscv.li 0 : () -> !riscv.reg<zero>
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I think the anonymous ssa value here actually makes it harder to read the test

@superlopuh superlopuh merged commit d2569e9 into main May 28, 2024
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@superlopuh superlopuh deleted the sasha/riscv/regalloc-lb-ub-step branch May 28, 2024 20:42
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3 participants