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dialects: Implement MemoryEffect on RISCV op, just reuse main CSE. #2685

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merged 7 commits into from
Jun 27, 2024

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PapyChacal
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Remove the riscv-cse pass, instead implement AllocatedMemoryEffect on some RISCV ops and let generic CSE do the job.

This makes CSE more powerful, with dead-code elimination and common subexpression elimination across regions.

@PapyChacal PapyChacal added dialects Changes on the dialects transformations Changes or adds a transformatio labels Jun 3, 2024
@PapyChacal PapyChacal requested a review from superlopuh June 3, 2024 10:12
@PapyChacal PapyChacal self-assigned this Jun 3, 2024
Comment on lines 14 to 20
"test.op"(%d8, %e8) : (!riscv.reg<>, !riscv.reg<>) -> ()
}

%f8 = riscv.li 8 : () -> !riscv.reg<>

"test.op"(%a8, %b8, %c8, %a7, %a7, %b7, %f8) : (!riscv.reg<>, !riscv.reg<>, !riscv.reg<>, !riscv.reg<>, !riscv.reg<>, !riscv.reg<>, !riscv.reg<>) -> ()

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Added two test.ops to use value and prevent CSE to rightfully CSE away the whole module

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codecov bot commented Jun 3, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 89.77%. Comparing base (f8834ad) to head (065fb39).
Report is 1 commits behind head on main.

Additional details and impacted files
@@            Coverage Diff             @@
##             main    #2685      +/-   ##
==========================================
- Coverage   89.79%   89.77%   -0.02%     
==========================================
  Files         384      385       +1     
  Lines       48442    48490      +48     
  Branches     7429     7436       +7     
==========================================
+ Hits        43497    43534      +37     
- Misses       3781     3786       +5     
- Partials     1164     1170       +6     

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Fantastico

@PapyChacal PapyChacal marked this pull request as ready for review June 3, 2024 11:46
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Why only add the trait to two of the operations? Shouldn't this work for all RISC-V operations? And don't we also want to model memory effects to all load and stores?

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Why only add the trait to two of the operations? Shouldn't this work for all RISC-V operations?

Left as an exercise for the reader I guess; I see this is enough to do what's tested, but I don't know every corner of this dialect stack. Feel free to add the trait to any missing operation you see!

And don't we also want to model memory effects to all load and stores?

What do you mean by that? If you mean modelling read/write effects in more detail, yes, this is left as further work. I can help with if it would be useful somewhere specifically?

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I would say that this is good to merge as-is, in an incomplete state, we can fill in the rest of the ops with the effect later.

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I would say that this is good to merge as-is, in an incomplete state, we can fill in the rest of the ops with the effect later.

Alright, will update and merge soonish 🙂

@@ -75,7 +80,6 @@ riscv_scf.for %13 : !riscv.reg = %11 to %8 step %12 {
// CHECK-NEXT: %{{.*}} = riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} iter_args(%{{.*}} = %{{.*}}) -> (!riscv.freg) {
// CHECK-NEXT: %{{.*}} = riscv_snitch.read from %{{.*}} : !riscv.freg
// CHECK-NEXT: %{{.*}} = riscv_snitch.read from %{{.*}} : !riscv.freg
// CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
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oh actually this is weird

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Just so no-one merges accidentally, this is currently not working.

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Just so no-one merges accidentally, this is currently not working.

We called and this was about a misread of the test-case: An unused operation was correctly erased, the example simply intended to have it used instead.

@superlopuh superlopuh merged commit 33ce696 into main Jun 27, 2024
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@superlopuh superlopuh deleted the emilien/riscv-cse branch June 27, 2024 16:38
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3 participants