backend: reserve registers not preserved across function calls in RISC-V #2853
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #2853 +/- ##
==========================================
- Coverage 89.89% 89.89% -0.01%
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Files 398 398
Lines 49659 49674 +15
Branches 7633 7634 +1
==========================================
+ Hits 44641 44654 +13
- Misses 3821 3822 +1
- Partials 1197 1198 +1 ☔ View full report in Codecov by Sentry. |
zero9178
approved these changes
Jul 6, 2024
| @@ -26,6 +26,12 @@ def gather_allocated(func: riscv_func.FuncOp) -> set[RISCVRegisterType]: | |||
| if not isinstance(op, RISCVAsmOperation): | |||
| continue | |||
|
|
|||
| if isinstance(op, riscv_func.CallOp): | |||
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Probably worth putting a command here as to why this is done for whoever is going to implement call ABI to find and remove this.
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A little correctness improvement, we should only be allocating to s registers if there's a function call, of which there should be 0 for the foreseeable future, but it's nice not to silently miscompile.