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dialects: (snitch_stream) add custom syntax to streaming region #2859

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Jul 7, 2024
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dialects: (snitch_stream) add custom syntax to streaming region #2859

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5daf5f6
dialects: (snitch_stream) add custom syntax to streaming region
superlopuh Jul 7, 2024
1160414
use attributes to mark attributes
superlopuh Jul 7, 2024
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32 changes: 18 additions & 14 deletions tests/filecheck/dialects/snitch_stream/ops.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,11 @@

%X, %Y, %Z = "test.op"() : () -> (!riscv.reg, !riscv.reg, !riscv.reg)

"snitch_stream.streaming_region"(%X, %Y, %Z) <{
"stride_patterns" = [#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>],
"operandSegmentSizes" = array<i32: 2, 1>
}> ({
snitch_stream.streaming_region {
stride_patterns = [
#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>
]
} ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
%c5 = riscv.li 5 : !riscv.reg
riscv_snitch.frep_outer %c5 {
Expand All @@ -15,21 +16,24 @@
%c = riscv.fadd.d %a, %b : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft2>
riscv_snitch.write %c to %c_stream : !riscv.freg<ft2>
}
}) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
}


// CHECK: %X, %Y, %Z = "test.op"() : () -> (!riscv.reg, !riscv.reg, !riscv.reg)
// CHECK-NEXT: "snitch_stream.streaming_region"(%X, %Y, %Z) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
// CHECK-NEXT: ^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
// CHECK-NEXT: %c5 = riscv.li 5 : !riscv.reg
// CHECK-NEXT: riscv_snitch.frep_outer %c5 {
// CHECK-NEXT: %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
// CHECK-NEXT: %b = riscv_snitch.read from %b_stream : !riscv.freg<ft1>
// CHECK-NEXT: %c = riscv.fadd.d %a, %b : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft2>
// CHECK-NEXT: riscv_snitch.write %c to %c_stream : !riscv.freg<ft2>
// CHECK-NEXT: %c5 = riscv.li 5 : !riscv.reg
// CHECK-NEXT: riscv_snitch.frep_outer %c5 {
// CHECK-NEXT: %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
// CHECK-NEXT: %b = riscv_snitch.read from %b_stream : !riscv.freg<ft1>
// CHECK-NEXT: %c = riscv.fadd.d %a, %b : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft2>
// CHECK-NEXT: riscv_snitch.write %c to %c_stream : !riscv.freg<ft2>
// CHECK-NEXT: }
// CHECK-NEXT: }
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()


// CHECK-GENERIC: %X, %Y, %Z = "test.op"() : () -> (!riscv.reg, !riscv.reg, !riscv.reg)
// CHECK-GENERIC-NEXT: "snitch_stream.streaming_region"(%X, %Y, %Z) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
Expand Down
148 changes: 89 additions & 59 deletions tests/filecheck/transforms/convert_memref_stream_to_snitch.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -30,16 +30,22 @@ memref_stream.streaming_region {
}

// CHECK-NEXT: %A, %B, %C = "test.op"() : () -> (memref<2xf64>, memref<3xf64>, memref<3x2xf64>)
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %A : memref<2xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %B : memref<3xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}, %{{.*}}, %{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [3, 2], strides = [8, 0]>, #snitch_stream.stride_pattern<ub = [3, 2], strides = [0, 8]>, #snitch_stream.stride_pattern<ub = [6], strides = [8]>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
// CHECK-NEXT: ^0(%a : !stream.readable<!riscv.freg>, %b : !stream.readable<!riscv.freg>, %c : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %a : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %b : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %c : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: "test.op"(%{{.*}}, %{{.*}}, %{{.*}}) : (!stream.readable<f64>, !stream.readable<f64>, !stream.writable<f64>) -> ()
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %A_1 = builtin.unrealized_conversion_cast %A : memref<2xf64> to !riscv.reg
// CHECK-NEXT: %B_1 = builtin.unrealized_conversion_cast %B : memref<3xf64> to !riscv.reg
// CHECK-NEXT: %C_1 = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [3, 2], strides = [8, 0]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [3, 2], strides = [0, 8]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [6], strides = [8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%A_1, %B_1 : !riscv.reg, !riscv.reg) outs(%C_1 : !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%a : !stream.readable<!riscv.freg>, %b : !stream.readable<!riscv.freg>, %c : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %a_1 = builtin.unrealized_conversion_cast %a : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %b_1 = builtin.unrealized_conversion_cast %b : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %c_1 = builtin.unrealized_conversion_cast %c : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: "test.op"(%a_1, %b_1, %c_1) : (!stream.readable<f64>, !stream.readable<f64>, !stream.writable<f64>) -> ()
// CHECK-NEXT: }

memref_stream.streaming_region {
patterns = [
Expand All @@ -51,15 +57,18 @@ memref_stream.streaming_region {
"test.op"(%c0, %c1) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
}

// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}, %{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [6], strides = [8]>], "operandSegmentSizes" = array<i32: 2, 0>}> ({
// CHECK-NEXT: ^{{.*}}(%c0 : !stream.readable<!riscv.freg>, %c1 : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %c0 : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %c1 : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%{{.*}}, %{{.*}}) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg) -> ()

// CHECK-NEXT: %C_2 = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: %C_3 = builtin.unrealized_conversion_cast %C : memref<3x2xf64> to !riscv.reg
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [6], strides = [8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%C_2, %C_3 : !riscv.reg, !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%c0 : !stream.readable<!riscv.freg>, %c1 : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %c0_1 = builtin.unrealized_conversion_cast %c0 : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %c1_1 = builtin.unrealized_conversion_cast %c1 : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%c0_1, %c1_1) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }

%D, %E = "test.op"() : () -> (memref<1x1x8x8xf64>, memref<1x1x3x3xf64>)
// CHECK-NEXT: %D, %E = "test.op"() : () -> (memref<1x1x8x8xf64>, memref<1x1x3x3xf64>)
Expand All @@ -74,14 +83,19 @@ memref_stream.streaming_region {
"test.op"(%d_stream, %e_stream) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
}

// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<1x1x8x8xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<1x1x3x3xf64> to !riscv.reg
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}, %{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [6, 6, 3, 3], strides = [64, 8, 64, 8]>, #snitch_stream.stride_pattern<ub = [36, 3, 3], strides = [0, 24, 8]>], "operandSegmentSizes" = array<i32: 2, 0>}> ({
// CHECK-NEXT: ^{{.*}}(%{{.*}} : !stream.readable<!riscv.freg>, %{{.*}} : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%{{.*}}, %{{.*}}) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %D_1 = builtin.unrealized_conversion_cast %D : memref<1x1x8x8xf64> to !riscv.reg
// CHECK-NEXT: %E_1 = builtin.unrealized_conversion_cast %E : memref<1x1x3x3xf64> to !riscv.reg
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [6, 6, 3, 3], strides = [64, 8, 64, 8]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [36, 3, 3], strides = [0, 24, 8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%D_1, %E_1 : !riscv.reg, !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%d_stream : !stream.readable<!riscv.freg>, %e_stream : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %d_stream_1 = builtin.unrealized_conversion_cast %d_stream : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %e_stream_1 = builtin.unrealized_conversion_cast %e_stream : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%d_stream_1, %e_stream_1) : (!stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }

%F = "test.op"() : () -> memref<8x8xf64>
// CHECK-NEXT: %F = "test.op"() : () -> memref<8x8xf64>
Expand All @@ -97,16 +111,22 @@ memref_stream.streaming_region {
"test.op"(%x_stream, %w_stream, %b_stream) : (!stream.readable<f64>, !stream.readable<f64>, !stream.readable<f64>) -> ()
}

// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}, %{{.*}}, %{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [8, 8, 8], strides = [64, 0, 8]>, #snitch_stream.stride_pattern<ub = [8, 8, 8], strides = [0, 8, 64]>, #snitch_stream.stride_pattern<ub = [64], strides = [8]>], "operandSegmentSizes" = array<i32: 3, 0>}> ({
// CHECK-NEXT: ^{{.*}}(%{{.*}} : !stream.readable<!riscv.freg>, %{{.*}} : !stream.readable<!riscv.freg>, %{{.*}} : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%{{.*}}, %{{.*}}, %{{.*}}) : (!stream.readable<f64>, !stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: %F_1 = builtin.unrealized_conversion_cast %F : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: %F_2 = builtin.unrealized_conversion_cast %F : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: %F_3 = builtin.unrealized_conversion_cast %F : memref<8x8xf64> to !riscv.reg
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [8, 8, 8], strides = [64, 0, 8]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [8, 8, 8], strides = [0, 8, 64]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [64], strides = [8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%F_1, %F_2, %F_3 : !riscv.reg, !riscv.reg, !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%x_stream : !stream.readable<!riscv.freg>, %w_stream : !stream.readable<!riscv.freg>, %b_stream : !stream.readable<!riscv.freg>):
// CHECK-NEXT: %x_stream_1 = builtin.unrealized_conversion_cast %x_stream : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %w_stream_1 = builtin.unrealized_conversion_cast %w_stream : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %b_stream_1 = builtin.unrealized_conversion_cast %b_stream : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: "test.op"(%x_stream_1, %w_stream_1, %b_stream_1) : (!stream.readable<f64>, !stream.readable<f64>, !stream.readable<f64>) -> ()
// CHECK-NEXT: }

%G, %H = "test.op"() : () -> (f64, memref<16x16xf64>)
// CHECK-NEXT: %G, %H = "test.op"() : () -> (f64, memref<16x16xf64>)
Expand All @@ -125,26 +145,30 @@ memref_stream.streaming_region {
}
}

// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : memref<16x16xf64> to !riscv.reg
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [256], strides = [8]>], "operandSegmentSizes" = array<i32: 0, 1>}> ({
// CHECK-NEXT: ^{{.*}}(%{{.*}} : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: %{{.*}} = arith.constant 0 : i32
// CHECK-NEXT: %{{.*}} = arith.constant 1 : i32
// CHECK-NEXT: %{{.*}} = arith.constant 256 : i32
// CHECK-NEXT: scf.for %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} : i32 {
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.writable<f64> to !stream.writable<!riscv.freg>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : f64 to !riscv.freg
// CHECK-NEXT: %H_1 = builtin.unrealized_conversion_cast %H : memref<16x16xf64> to !riscv.reg
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [256], strides = [8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } outs(%H_1 : !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%h_stream : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %h_stream_1 = builtin.unrealized_conversion_cast %h_stream : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: %c0_2 = arith.constant 0 : i32
// CHECK-NEXT: %c1_2 = arith.constant 1 : i32
// CHECK-NEXT: %c256 = arith.constant 256 : i32
// CHECK-NEXT: scf.for %i = %c0_2 to %c256 step %c1_2 : i32 {
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %h_stream_1 : !stream.writable<f64> to !stream.writable<!riscv.freg>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %G : f64 to !riscv.freg
// CHECK-NEXT: %{{.*}} = riscv.fmv.d %{{.*}} : (!riscv.freg) -> !riscv.freg
// CHECK-NEXT: riscv_snitch.write %{{.*}} to %{{.*}} : !riscv.freg
// CHECK-NEXT: }
// CHECK-NEXT: }) : (!riscv.reg) -> ()
// CHECK-NEXT: }

%I, %J, %K = "test.op"() : () -> (memref<3x5xf64>, memref<5x8xf64>, memref<3x8xf64>)
// CHECK-NEXT: %I, %J, %K = "test.op"() : () -> (memref<3x5xf64>, memref<5x8xf64>, memref<3x8xf64>)
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %I : memref<3x5xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %J : memref<5x8xf64> to !riscv.reg
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %K : memref<3x8xf64> to !riscv.reg
// CHECK-NEXT: %I_1 = builtin.unrealized_conversion_cast %I : memref<3x5xf64> to !riscv.reg
// CHECK-NEXT: %J_1 = builtin.unrealized_conversion_cast %J : memref<5x8xf64> to !riscv.reg
// CHECK-NEXT: %K_1 = builtin.unrealized_conversion_cast %K : memref<3x8xf64> to !riscv.reg

// more complex maps
memref_stream.streaming_region {
Expand All @@ -158,13 +182,19 @@ memref_stream.streaming_region {
%res = "test.op"() : () -> f64
memref_stream.yield %res : f64
}
// CHECK-NEXT: "snitch_stream.streaming_region"(%{{.*}}, %{{.*}}, %{{.*}}) <{"stride_patterns" = [#snitch_stream.stride_pattern<ub = [3, 2, 5, 4], strides = [40, 0, 8, 0]>, #snitch_stream.stride_pattern<ub = [3, 2, 5, 4], strides = [0, 32, 64, 8]>, #snitch_stream.stride_pattern<ub = [24], strides = [8]>], "operandSegmentSizes" = array<i32: 2, 1>}> ({
// CHECK-NEXT: ^{{.*}}(%{{.*}} : !stream.readable<!riscv.freg>, %{{.*}} : !stream.readable<!riscv.freg>, %{{.*}} : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %{{.*}} = builtin.unrealized_conversion_cast %{{.*}} : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: %{{.*}} = "test.op"() : () -> f64
// CHECK-NEXT: memref_stream.yield %{{.*}} : f64
// CHECK-NEXT: }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
// CHECK-NEXT: snitch_stream.streaming_region {
// CHECK-NEXT: patterns = [
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [3, 2, 5, 4], strides = [40, 0, 8, 0]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [3, 2, 5, 4], strides = [0, 32, 64, 8]>,
// CHECK-NEXT: #snitch_stream.stride_pattern<ub = [24], strides = [8]>
// CHECK-NEXT: ]
// CHECK-NEXT: } ins(%I_1, %J_1 : !riscv.reg, !riscv.reg) outs(%K_1 : !riscv.reg) {
// CHECK-NEXT: ^{{.*}}(%i_1 : !stream.readable<!riscv.freg>, %j : !stream.readable<!riscv.freg>, %k : !stream.writable<!riscv.freg>):
// CHECK-NEXT: %i_2 = builtin.unrealized_conversion_cast %i_1 : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %j_1 = builtin.unrealized_conversion_cast %j : !stream.readable<!riscv.freg> to !stream.readable<f64>
// CHECK-NEXT: %k_1 = builtin.unrealized_conversion_cast %k : !stream.writable<!riscv.freg> to !stream.writable<f64>
// CHECK-NEXT: %res = "test.op"() : () -> f64
// CHECK-NEXT: memref_stream.yield %res : f64
// CHECK-NEXT: }

// CHECK-NEXT: }
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