backend: add RegisterConstraints and use in riscv backend #2930
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #2930 +/- ##
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Coverage 89.92% 89.93%
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Files 405 406 +1
Lines 50597 50646 +49
Branches 7823 7826 +3
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+ Hits 45497 45546 +49
Misses 3868 3868
Partials 1232 1232 ☔ View full report in Codecov by Sentry. |
zero9178
approved these changes
Jul 23, 2024
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This is required for some of the vector operations in riscv that reuse the rd register as an operand.