misc: fix arguments for riscv_lowering

[oluwatimilehin]

@superlopuh Fixing some potential bugs I encountered while using xDSL as a backend

[compor]

this looks like a bug? maybe our funcs were void so far? could you please add a test case for this?
let us know if you need a hand

[oluwatimilehin]

Hey Chris, how would you recommend I test this? It looks like I need to modify line 6 here, but I am not sure how to exercise this change and don't remember how I encountered the bug :(

What do you have in mind?

[superlopuh]

Just modifying it to be (i32, f32) -> (i64, f64) should be enough

[oluwatimilehin]

Do you mean doing this:

    func.func @main() {
        %0, %1 = "test.op"() : () -> (i32, f32)
        %2, %3 = func.call @foo(%0, %1) : (i32, f32) -> (i64, f64)
        func. return
    }

Which I suppose will require changing foo() too to accept an f32 type:

    func.func @foo(%arg0 : i32, %arg1 : i32) -> (i32, i32) {
        %res0, %res1 = "test.op"(%arg0, %arg1) : (i32, i32) -> (i32, i32)
        func.return %res0, %res1 : i32, i32
    }

Is that right?

[superlopuh]

yeah these would all have to be consistent within the file but that's the essence of the change

[compor]

thanks for splitting the PRs btw

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 91.29%. Comparing base (7be8c6f) to head (d5b7415).
Report is 11 commits behind head on main.

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #3900      +/-   ##
==========================================
+ Coverage   91.26%   91.29%   +0.03%     
==========================================
  Files         466      466              
  Lines       57960    58012      +52     
  Branches     5567     5566       -1     
==========================================
+ Hits        52897    52962      +65     
+ Misses       3639     3622      -17     
- Partials     1424     1428       +4     

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[oluwatimilehin]

This fixes a bug here that makes it raise an error for floating point registers:

xdsl/xdsl/backend/riscv/lowering/utils.py

Lines 57 to 67 in 6f2c376

	elif isinstance(rd, riscv.FloatRegisterType):
	match value_type:
	case builtin.Float64Type():
	mv_op = riscv.FMvDOp(value, rd=rd)
	case builtin.Float32Type():
	mv_op = riscv.FMVOp(value, rd=rd)
	case _:
	raise NotImplementedError(
	f"Move operation for float register containing value of type {value.type} is not implemented"
	)
	return mv_op, mv_op.rd

value_type in the original code is neither of the two.

[superlopuh]

what is it?

[oluwatimilehin]

It's a FloatRegisterType.