backend: (riscv) split out reserved int and float registers in regalloc

[superlopuh]

This is the only part of the RiscvRegisterQueue that mixes the two register types, this split is necessary to make the more fundamental split into two register queues.

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 91.30%. Comparing base (c6a58b2) to head (5ff175f).
Report is 1 commits behind head on main.

Additional details and impacted files

@@           Coverage Diff           @@
##             main    #3927   +/-   ##
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  Coverage   91.30%   91.30%           
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  Files         467      467           
  Lines       58053    58065   +12     
  Branches     5575     5580    +5     
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+ Hits        53006    53017   +11     
  Misses       3617     3617           
- Partials     1430     1431    +1     

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[compor]

Where is this heading? I assume 2 independent queues or a queue per register type.

[superlopuh]

First the first thing then the second thing, exactly :)

[superlopuh]

That will get us closer to structures that we can reuse for the other backends