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arm: Replace arm_builtin_vectorized_function [PR106253]
This patch extends the fix for PR106253 to AArch32. As with AArch64,
we were using ACLE intrinsics to vectorise scalar built-ins, even
though the two sometimes have different ECF_* flags. (That in turn
is because the ACLE intrinsics should follow the instruction semantics
as closely as possible, whereas the scalar built-ins follow language
specs.)
The patch also removes the copysignf built-in, which only existed
for this purpose and wasn't a “real” arm_neon.h built-in.
Doing this also has the side-effect of enabling vectorisation of
rint and roundeven. Logically that should be a separate patch,
but making it one would have meant adding a new int iterator
for the original set of instructions and then removing it again
when including new functions.
I've restricted the bswap tests to little-endian because we end
up with excessive spilling on big-endian. E.g.:
sub sp, sp, gcc-mirror#8
vstr d1, [sp]
vldr d16, [sp]
vrev16.8 d16, d16
vstr d16, [sp]
vldr d0, [sp]
add sp, sp, gcc-mirror#8
@ sp needed
bx lr
Similarly, the copysign tests require little-endian because on
big-endian we unnecessarily load the constant from the constant pool:
vldr.32 s15, .L3
vdup.32 d0, d7[1]
vbsl d0, d2, d1
bx lr
.L3:
.word -2147483648
gcc/
PR target/106253
* config/arm/arm-builtins.cc (arm_builtin_vectorized_function):
Delete.
* config/arm/arm-protos.h (arm_builtin_vectorized_function): Delete.
* config/arm/arm.cc (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION):
Delete.
* config/arm/arm_neon_builtins.def (copysignf): Delete.
* config/arm/iterators.md (nvrint_pattern): New attribute.
* config/arm/neon.md (<NEON_VRINT:nvrint_pattern><VCVTF:mode>2):
New pattern.
(l<NEON_VCVT:nvrint_pattern><su_optab><VCVTF:mode><v_cmp_result>2):
Likewise.
(neon_copysignf<mode>): Rename to...
(copysign<mode>3): ...this.
gcc/testsuite/
PR target/106253
* gcc.target/arm/vect_unary_1.c: New test.
* gcc.target/arm/vect_binary_1.c: Likewise.- Loading branch information
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,50 @@ | ||
| /* { dg-do compile { target { arm*-*-* } } } */ | ||
| /* { dg-require-effective-target arm_hard_ok } */ | ||
| /* { dg-require-effective-target arm_v8_neon_ok } */ | ||
| /* { dg-add-options arm_v8_neon } */ | ||
| /* { dg-additional-options "-O3 -mfloat-abi=hard" } */ | ||
| /* { dg-final { check-function-bodies "**" "" "" } } */ | ||
|
|
||
| #include <stdint.h> | ||
|
|
||
| #define TEST2(OUT, NAME, IN) \ | ||
| OUT __attribute__((vector_size(sizeof(OUT) * 2))) \ | ||
| test2_##OUT##_##NAME##_##IN (float dummy, \ | ||
| IN __attribute__((vector_size(sizeof(IN) * 2))) y, \ | ||
| IN __attribute__((vector_size(sizeof(IN) * 2))) z) \ | ||
| { \ | ||
| OUT __attribute__((vector_size(sizeof(OUT) * 2))) x; \ | ||
| x[0] = __builtin_##NAME (y[0], z[0]); \ | ||
| x[1] = __builtin_##NAME (y[1], z[1]); \ | ||
| return x; \ | ||
| } | ||
|
|
||
| #define TEST4(OUT, NAME, IN) \ | ||
| OUT __attribute__((vector_size(sizeof(OUT) * 4))) \ | ||
| test4_##OUT##_##NAME##_##IN (float dummy, \ | ||
| IN __attribute__((vector_size(sizeof(OUT) * 4))) y, \ | ||
| IN __attribute__((vector_size(sizeof(OUT) * 4))) z) \ | ||
| { \ | ||
| OUT __attribute__((vector_size(sizeof(OUT) * 4))) x; \ | ||
| x[0] = __builtin_##NAME (y[0], z[0]); \ | ||
| x[1] = __builtin_##NAME (y[1], z[1]); \ | ||
| x[2] = __builtin_##NAME (y[2], z[2]); \ | ||
| x[3] = __builtin_##NAME (y[3], z[3]); \ | ||
| return x; \ | ||
| } | ||
|
|
||
| /* | ||
| ** test2_float_copysignf_float: { target arm_little_endian } | ||
| ** vmov.i32 d0, #(0x80000000|2147483648)(\s+.*) | ||
| ** vbsl d0, d2, d1 | ||
| ** bx lr | ||
| */ | ||
| TEST2 (float, copysignf, float) | ||
|
|
||
| /* | ||
| ** test4_float_copysignf_float: { target arm_little_endian } | ||
| ** vmov.i32 q0, #(0x80000000|2147483648)(\s+.*) | ||
| ** vbsl q0, q2, q1 | ||
| ** bx lr | ||
| */ | ||
| TEST4 (float, copysignf, float) |
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