Merge pull request #103 from shuchitak/feature/fix_tests

Fix test_i2s_basic_slave and test_slave_bclk_invert tests

test/lib_i2s/i2s_slave_checker.py

@@ -92,7 +92,7 @@ def run(self):
  xsi, self._setup_strobe_port, self._setup_data_port
  )
  xsi.drive_port_pins(self._bclk, bclk1)
- xsi.drive_port_pins(self._lrclk, 1)
+ xsi.drive_port_pins(self._lrclk, 0)
 
  bclk_frequency = (bclk_frequency_u << 16) + bclk_frequency_l
  print(
@@ -146,6 +146,10 @@ def run(self):
  # the range 32 - 63, lr_clock outputs 1, else it outputs 0.
  time = float(xsi.get_time())
 
+ time = self.wait_until_ret(
+ time + (clock_half_period * 64)
+ ) # Add extra delay to ensure that the i2s_slave device sees the LRCLK transitions in the first for loop below
+
  lr_counter = data_bits + (data_bits // 2) + (is_i2s_justified)
  lr_count_max = (2 * data_bits) - 1
 
@@ -213,7 +217,7 @@ def run(self):
  time = self.wait_until_ret(
  time + clock_half_period - din_sample_offset
  )
- 
+
  data_bit_mask = int("1" * data_bits, base=2)
 
  for p in range(0, num_outs):

test/lib_i2s/i2s_slave_test/i2s_slave_test.cmake

@@ -16,6 +16,10 @@ set(APP_LINK_OPTIONS
  -target=XCORE-AI-EXPLORER
 )
 
+# Compile main.c which contains the i2s_callback_group_t functions in O3 mode. Needed for passing the
+# test_i2s_basic_slave[4ch_in,4ch_out-32b] and test_i2s_basic_slave[4ch_in,4ch_out-16b] tests
+set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/src/main.c PROPERTIES COMPILE_FLAGS "-O3")
+
 #**********************
 # Tile Targets
 #**********************

test/lib_i2s/i2s_slave_test/src/main.c

@@ -23,17 +23,14 @@ xclock_t bclk = XS1_CLKBLK_1;
 #define I2S_LOOPBACK_LATENCY 1
 
 #if SMOKE == 1
-#define NUM_BCLKS 1
-#define NUM_BCLKS_TO_CHECK 1
-static const unsigned bclk_freq_lut[NUM_BCLKS] = {
- 1228800
+#define NUM_LRCLKS_TO_CHECK 1
+static const unsigned lr_freq_lut[] = {
+ 192000
 };
 #else
-#define NUM_BCLKS 12
-#define NUM_BCLKS_TO_CHECK 3
-static const unsigned bclk_freq_lut[NUM_BCLKS] = {
- 1228800, 614400, 384000, 192000, 44100,
- 22050, 96000, 176400, 88200, 48000, 24000, 352800
+#define NUM_LRCLKS_TO_CHECK 6
+static const unsigned lr_freq_lut[] = {
+ 192000, 176400, 96000, 88200, 48000, 44100
 };
 #endif
 #ifndef DATA_BITS
@@ -111,7 +108,7 @@ static int request_response(
  return r;
 }
 
-static unsigned bclk_freq_index = 0;
+static unsigned lr_freq_index = 0;
 static unsigned frames_sent = 0;
 static unsigned rx_data_counter[MAX_CHANNELS] = {0};
 static unsigned tx_data_counter[MAX_CHANNELS] = {0};
@@ -150,8 +147,9 @@ i2s_restart_t i2s_restart_check(void *app_data)
  i2s_restart_t restart;
 
  frames_sent++;
- if (frames_sent == 4)
+ if (frames_sent == 4) {
  restart = I2S_RESTART;
+ }
  else
  restart = I2S_NO_RESTART;
 
@@ -173,15 +171,15 @@ void i2s_init(void *app_data, i2s_config_t *i2s_config)
  printf("Error\n");
  }
 
- if (bclk_freq_index == NUM_BCLKS_TO_CHECK - 1) {
+ if (lr_freq_index == NUM_LRCLKS_TO_CHECK - 1) {
  if (current_mode == I2S_MODE_I2S) {
  current_mode = I2S_MODE_LEFT_JUSTIFIED;
- bclk_freq_index = 0;
+ lr_freq_index = 0;
  } else {
  _Exit(1);
  }
  } else {
- bclk_freq_index++;
+ lr_freq_index++;
  }
  }
 
@@ -196,7 +194,9 @@ void i2s_init(void *app_data, i2s_config_t *i2s_config)
  rx_data_counter[i] = 0;
  }
 
- broadcast(bclk_freq_lut[bclk_freq_index],
+ unsigned bclk_freq = lr_freq_lut[lr_freq_index] * DATA_BITS * I2S_CHANS_PER_FRAME;
+
+ broadcast(bclk_freq,
  NUM_IN,
  NUM_OUT, DATA_BITS, i2s_config->mode == I2S_MODE_I2S);
 

test/lib_i2s/test_i2s_basic_slave.py

@@ -10,6 +10,7 @@
 
 num_in_out_args = {
  "4ch_in,4ch_out": (4, 4),
+ "2ch_in,2ch_out": (2, 2),
  "1ch_in,1ch_out": (1, 1),
  "4ch_in,0ch_out": (4, 0),
  "0ch_in,4ch_out": (0, 4),

test/lib_i2s/test_slave_bclk_invert.py

@@ -6,7 +6,13 @@
 import pytest
 import Pyxsim as px
 
-num_in_out_args = {"2ch_in,2ch_out": (2, 2)}
+num_in_out_args = {
+ "4ch_in,4ch_out": (4, 4),
+ "2ch_in,2ch_out": (2, 2),
+ "1ch_in,1ch_out": (1, 1),
+ "4ch_in,0ch_out": (4, 0),
+ "0ch_in,4ch_out": (0, 4),
+}
 
 bitdepth_args = {"16b": 16, "32b": 32}