Extending sw_pll to monitor PFD error stability not possible due to host cycling through SRs in dig Rx config

[ed-xmos]

The MAC host cycles through SRs to check clock validity for each of the supported SRs.
When using a digital receive the sw_pll PI controller clearly cannot converge due to the received sample rate of dig rx not matching the selected sample rate.
@xross says that currently we use a delay to assume the CS2100 is locked but with sw_pll we can measure the raw error to see when it has locked (it will tend to zero). This method would allow a reliable way of knowing when to release Audio and ensure no buffer ends are hit. It works for sync mode but cannot currently work for dig rx due to this SR cycling by the host.
It would need extra logic to disable waiting for the error to converge unless dig rx SR == selected SR.

The WIP code for this feature can be found here #365