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Andes/v6.1.80 #1

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a1192a6
riscv: andes: add ae350 platform to SoC
lyctw Oct 17, 2022
1aa093c
riscv: andes: defconfig: add andes_defconfig and andes-support.config
Feb 1, 2023
6f58fc1
riscv: andes: Add Andes-specific relocation type
NonerKao Oct 16, 2019
9e95b4a
riscv: andes: add new readl_fixup() when driver probing
lyctw Aug 2, 2022
855a734
soc: andes: add andes platform csr.h and proc.h and sbi.h
Dec 13, 2022
9b1a034
riscv: andes: add Andes alternative ports
Oct 27, 2022
16180fc
riscv: andes: legacy_mmu: apply errata legacy MMU patch
Nov 1, 2022
0c67615
soc: andes: cache: add Andes cache support
Dec 13, 2022
e159bf6
riscv: andes: Implement ioremap_wc for noncached memory remapping sup…
Mar 7, 2023
b431461
riscv: andes: support physical address MSB
Mar 3, 2023
40aa955
soc: andes: ppma: support Andes PPMA(Programmable Physical Memory Att…
Mar 7, 2023
1348154
soc: andes: dma-noncoherent: add Andes dma-noncoherent
Mar 8, 2023
5768a16
dmaengine: andes: atcdmac300g: Andes support DMA engine
Oct 14, 2021
26c6078
mmc: andes: ftsdc010g: add andes ftsdc010g
Oct 14, 2021
8198e01
mmc: andes: ftsdc010g: add new readl_fixup() when driver probing
Oct 14, 2021
3e0956d
net: andes: ftmac100: Andes support for Faraday ATCMAC
NonerKao Sep 3, 2019
5a6888d
net: andes: ftmac100: add new readl_fixup() when driver probing
lyctw Aug 2, 2022
5c1393c
RISC-V: mm: Support huge page in vmalloc_fault()
Dylan-Jhong Feb 24, 2023
f558c5b
riscv: andes: fix ex_table mismatch
Mar 22, 2023
4e4da59
soc: andes: cache: Remove unused l2c functions
Apr 11, 2023
1ef886f
soc: andes: cache: remove andes userspace cache and M-mode control fu…
Apr 27, 2023
83514c6
riscv: andes: defconfig: set RISCV SBI earlycon config to enable in a…
Apr 13, 2023
f1e04e6
riscv: Allow to downgrade paging mode from the command line
Apr 24, 2023
bafbf13
riscv: Kconfig: Enable cpufreq kconfig menu
prabhakarlad Nov 15, 2022
a1ae710
riscv: andes: defconfig: enable CONFIG_CPU_FREQ for andes_defconfig
May 3, 2023
92fa498
soc: andes: ppma: Support IPI in andes_free_ppma()
Dylan-Jhong Apr 28, 2023
168d9e0
soc: andes: injection: Andes support injection feature
Apr 17, 2023
bc874ac
soc: andes: injection: upgrade struct file_operations to struct proc_ops
Apr 17, 2023
12f5269
riscv: andes: dsp: DSP support
Apr 20, 2023
6c6f1c2
rtc: andes: atcrtc100: Andes support for ATCRTC
Nov 30, 2021
0baa867
rtc: andes: atcrtc100: add new readl_fixup() when driver probing
May 5, 2023
56a9dbb
soc: andes: ppma: fix complier error when disable ppma
May 11, 2023
46eec23
pwm: andes: atcpit100: add Andes's PWM module
randolph-lin May 9, 2023
5dfd1ab
i2c: andes: atciic100: add Andes's I2C module
randolph-lin May 9, 2023
9b7b1ee
dmaengine: andes: atcdmac300g: support cyclic mode
Apr 26, 2023
c469912
soc: andes: atcdmac300: Support for legacy DMA engine
May 2, 2023
f80f552
mmc: andes: ftsdc010: support legacy MMC driver
May 9, 2023
4a8c168
sound: andes: ftssp010: Support for audio playback through legacy DMAC.
May 9, 2023
9ea8219
fbdev: andes: ftlcdc100: Update kernel configuration to support the f…
Apr 27, 2023
67a6417
soc: andes: atcdmac300: fix channel pending when burn-in the dmac driver
May 19, 2023
4fed16b
riscv: andes: defconfig: enable CONFIG_HZ_100 for andes_defconfig
Mina-Chou May 12, 2023
3ca3749
net: andes: ftmac100: use casting of u64 to avoid overflow
Dylan-Jhong May 19, 2023
61cc417
soc: andes: injection: injection script should adhere to the rules of…
May 23, 2023
85803cf
rtc: andes: atcrtc100: change reads the RTC four times to one time
May 23, 2023
c2be1a1
fbdev: andes: ftlcdc100: change OSD_putc if...else to switch
May 23, 2023
a63ba1b
scripts: andes: headers_install.sh : Add CONFIG_DSP in the leak ignor…
cynthia0928 Nov 3, 2021
ea591b8
soc: andes: pm: Add Andes power management support
May 26, 2023
6f9bc98
soc: andes: atcsmu: Add ATCSMU light/deep sleep support
May 26, 2023
5105fba
watchdog: andes: atcwdt200: Andes support for ATCWDT200
randolph-lin May 18, 2023
fb49f1f
gpio: andes: atcgpio100: Support Andes ATCGPIO100
May 23, 2023
2b6caa7
riscv: andes: defconfig: enable ATCGPIO100 for andes-support.config
May 23, 2023
92043e4
spi: andes: atcspi200: Support Andes ATCSPI200
May 23, 2023
81711ef
riscv: andes: defconfig: add sv39.config and sv48.config to support s…
May 25, 2023
2a3f313
v3PR: add earlycon=sbi to extend cmdline
Jun 9, 2023
907992b
riscv: andes: Kconfig: Disable CONFIG_STRICT_KERNEL_RWX
Jun 6, 2023
adde7c9
v3PR: CONFIG_STRICT_KERNEL_RWX=n
Jun 9, 2023
27530db
riscv: andes: Add Andes-specific NORVC relocation type
Mina-Chou May 26, 2023
db22aa6
fbdev: andes: ftlcdc100: Change the default LCD panel type from CONFI…
Jun 2, 2023
ff77207
net: andes: ftmac100: allow setting mac address by device tree
lyctw Dec 27, 2022
0e3a67f
soc: andes: dma-noncoherent: select ARCH_HAS_DMA_CLEAR_UNCACHED to su…
May 31, 2023
d40850a
riscv: dts: andes: ae350: Add initial Andes ae350 device tree
lyctw Oct 17, 2022
7137e6f
fbdev: andes: ftlcdc100: To support AUA036QN01, change the FFB mode f…
Jun 9, 2023
59457da
i2c: andes: atciic100: Set the nr to -1 to dynamically assign bus IDs…
Jun 9, 2023
6bc2668
drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9…
mmind Oct 11, 2022
4d02c54
RISC-V: Cache SBI vendor values
mmind Oct 11, 2022
652b40c
RISC-V: Create unique identification for SoC PMU
maquefel Aug 15, 2022
2d380c0
drivers/perf: RISC-V: Allow programming custom firmware events
mdchitale Feb 8, 2023
036dcc1
riscv: andes: add support for HPM variant on Andes
Jan 9, 2023
c1c2390
riscv: andes: defconfig: add config and include for Andes riscv pmu
Apr 7, 2023
3eedebd
riscv: andes: Fix the error for 32-bit perf
May 19, 2023
e7b3e61
riscv: andes: add Andes AX45 JSON file
Jan 18, 2023
41e44a1
tools: perf: andes: Add Andes L2C events to JSON files
lyctw May 11, 2023
7eb4740
perf/core: Implement workaround to add pmu stop before unthrottling t…
Jun 6, 2023
a515969
perf/core: Implement workaround to fix RCU stall issue when using per…
Jun 6, 2023
50041e0
tool/perf: Adjust the sample frequency to 1000
Jun 8, 2023
803957f
tool: andes: perf: fix perf tools compile error on Linux5.4
Jun 5, 2020
5ffbead
riscv: hwcap: Don't alphabetize ISA extension IDs
jones-drew Feb 9, 2023
c61d975
riscv: Support RISC-V Svnapot extension
jones-drew Dec 1, 2022
32f7ba7
posix_types.h: Add workaround fix for RV32 datatype "__kernel_off_t"
Dylan-Jhong Jun 19, 2023
d3eb093
riscv: andes: trigger_module: Support Andes trigger_module
Jun 2, 2023
bc20b3d
riscv: dts: andes: Set the full set dts for each core
Jun 30, 2023
127886a
riscv: andes: Support Andes supervisor detailed trap cause (sdcause)
NonerKao Oct 22, 2020
cbdeb33
riscv: amp: andes: add andes_remoteproc module
randolph-lin Jun 19, 2023
5ba384e
riscv: dts: andes: ae350: add amp device tree source for andes_remote…
randolph-lin Jun 9, 2023
3a9969b
riscv: fpu: refine FPU save flow
Sep 28, 2022
b6de3a2
riscv: andes: Fix WARN_ON when PROVE_LOCK is enabled
Jun 29, 2023
59ff4d4
soc: andes: ppma:Replacing smp_processor_id() with get/put_cpu() for …
Jul 18, 2023
0da0277
gpio: andes: atcgpio100: Support for the ngpios variable can be obtai…
Jul 6, 2023
51379c9
riscv: Implement flush_cache_vmap() and add a call to flush_cache_vma…
Jul 25, 2023
9e9d4a9
clocksource: andes: atcpit: Support Andes ATCPIT driver
Aug 8, 2023
6add1cb
clocksource: andes: atcpit: Refine ATCPIT driver
Aug 9, 2023
f4ee63c
clocksource: andes: atcpit: Refine the source code of the atcpit driver.
Aug 16, 2023
76868e2
perf cpumap: Make counter as unsigned ints
kraj Jan 23, 2023
519ad78
riscv: andes: Add AX45MPV 4-core device tree
lyctw Aug 10, 2023
55f0a9b
riscv: Move Andes DSP context switch out of __switch_to_aux
lyctw Aug 7, 2023
d621f79
RISC-V: Improve use of isa2hwcap[]
jones-drew Nov 29, 2022
3cb20fe
riscv: Rename __switch_to_aux() -> fpu
guoren83 Jun 5, 2023
7c9f4a4
riscv: Extending cpufeature.c to detect V-extension
guoren83 Jun 5, 2023
de54459
riscv: Add new csr defines related to vector extension
greentime Jun 5, 2023
4345ef2
riscv: Clear vector regfile on bootup
greentime Jun 5, 2023
bc854a3
riscv: Disable Vector Instructions for kernel itself
guoren83 Jun 5, 2023
34869e5
riscv: Introduce Vector enable/disable helpers
greentime Jun 5, 2023
3dac71f
riscv: Introduce riscv_v_vsize to record size of Vector context
greentime Jun 5, 2023
b577e07
riscv: Introduce struct/helpers to save/restore per-task Vector state
greentime Jun 5, 2023
86dc67b
riscv: Add task switch support for vector
greentime Jun 5, 2023
a8a9d7e
riscv: Allocate user's vector context in the first-use trap
AndybnACT Jun 5, 2023
03544b0
riscv: Add ptrace vector support
greentime Jun 5, 2023
667eba0
riscv: signal: check fp-reserved words unconditionally
AndybnACT Jun 5, 2023
99cbe63
riscv: signal: Add sigcontext save/restore for vector
greentime Jun 5, 2023
d9f5d36
riscv: signal: Report signal frame size to userspace via auxv
VincentZWC Jun 5, 2023
3c95c0f
riscv: signal: validate altstack to reflect Vector
AndybnACT Jun 5, 2023
02dcb69
riscv: prevent stack corruption by reserving task_pt_regs(p) early
greentime Jun 5, 2023
3c54498
riscv: kvm: Add V extension to KVM ISA
VincentZWC Jun 5, 2023
a90e220
riscv: KVM: Add vector lazy save/restore support
VincentZWC Jun 5, 2023
666aab6
riscv: hwcap: change ELF_HWCAP to a function
AndybnACT Jun 5, 2023
54ec507
riscv: Add prctl controls for userspace vector management
AndybnACT Jun 5, 2023
c3d7285
riscv: Add sysctl to set the default vector rule for new processes
AndybnACT Jun 5, 2023
9409efc
riscv: detect assembler support for .option arch
AndybnACT Jun 5, 2023
0fe85bb
riscv: Enable Vector code to be built
guoren83 Jun 5, 2023
4ef186f
riscv: Add documentation for Vector
AndybnACT Jun 5, 2023
df3898e
RISC-V: Remove ptrace support for vectors
palmer-dabbelt Aug 16, 2023
6fcfe8e
RISC-V: vector: export VLENB csr in __sc_riscv_v_state
AndybnACT Aug 16, 2023
142a943
riscv: vector: clear V-reg in the first-use trap
AndybnACT Jun 27, 2023
bb00166
andes: perf: add andes event to JSON file
Jul 31, 2023
b994db2
riscv: andes: defconfig: andes_defconfig default disable CONFIG_PREEMPT
Aug 1, 2023
3e73d7a
riscv: andes: Add RECOVER_UPSTREAM_CONFIG_RISCV to support upstream r…
Aug 3, 2023
aa6c8cc
riscv: andes: fix make failure with riscv generic defconfig
Aug 3, 2023
edece22
cpufreq: andes-cpufreq: Andes processors PowerBrake driver support
Aug 8, 2023
afbbde8
riscv: andes: remove config ANDES_QEMU_SUPPORT
Aug 9, 2023
f513b35
gpio: andes: atcgpio100: Fix recursive deadlock when setting the dire…
Sep 4, 2023
4f22a44
dmaengine: andes: atcdmac300g: Fix some typos
Aug 31, 2023
6065d72
clocksource: andes: atcpit: Refine the source code of the atcpit driver.
Aug 31, 2023
832e38b
andes: ftsdc010: Add another revision number
Sep 5, 2023
6fd3028
riscv: dts: andes: fix device node interrupt-parent
Sep 13, 2023
1e8a749
riscv: signal: fix sigaltstack frame size checking
AndybnACT Aug 22, 2023
a5a817c
RISC-V: Add ptrace support for vectors
AndybnACT Aug 25, 2023
f2c3d18
input: andes: touchscreen: Add the touch screen driver from the ast520.
Sep 7, 2023
ce738cb
input: andes: touchscreen: Refine the driver
Sep 7, 2023
8000a4a
riscv: andes: mm: Synchronize memory attributes for all mm in free_in…
Oct 16, 2023
707eaeb
riscv: andes: defconfig: enable CONFIG_PREEMPT allows failed LTP time…
Oct 19, 2023
bf71979
riscv: andes: a25mp: Add preempt disable/enable pair to prevent migra…
Oct 18, 2023
197c9d0
andes: perf: Fix event encoding of 0x32 on 25 and 65-series
lyctw Oct 25, 2023
1d86367
andes: perf: Add 27-series event encoding
lyctw Nov 1, 2023
76a9ba4
scripts/gdb: fix SB_* constants parsing
ffainelli Jun 7, 2023
87617c0
kselftest: Increase timeout value for andes platform
Mina-Chou Jul 25, 2023
51c0cd2
selftests/exec: Change the command interpreter of the shell script to…
Mina-Chou Jul 25, 2023
628e0f4
selftests/lkdtm: Remove the testcase that causes the system to hang.
Mina-Chou Jul 25, 2023
29b619f
selftests: Remove some unsupported commands by Busybox
Mina-Chou Jul 25, 2023
caed6e5
selftests/filesystems: Add six consecutive 'x' characters to mktemp
Mina-Chou Jul 18, 2023
247cfb8
selftest/zram: Specify block size as 4096 when mkfs on /dev/zram
Mina-Chou Sep 26, 2023
f5ce58b
selftests/kselftest_harness.h: Increase default timeout to 300 seconds
Mina-Chou Sep 26, 2023
1f9f2ce
Makefile: Exclude these test cases when kselftest-merge merges config
Mina-Chou Sep 5, 2023
9c4df00
selftests/ptrace: Remove the vmaccess test case.
Mina-Chou Oct 3, 2023
f76b5bf
selftests/Makefile: Add some test to SKIP_TARGETS
Mina-Chou Oct 4, 2023
290b327
selftests: Enable some required kernel config
Mina-Chou Nov 14, 2023
b8be07c
drivers: soc: andes: Add the "print_detailed_cause" method
Nov 1, 2023
8a6c6c9
drivers: soc: andes: Register the L2-cache IRQ
Dec 5, 2023
556ae28
drivers: soc: andes: Fix an error for print_detailed_cause() on impre…
Dec 26, 2023
3188aa7
IIC: andes: atciic100: Pass slave device DTS settings to the I2C fram…
Jan 3, 2024
6aa2342
RISC-V: Provide pgtable_l5_enabled on rv32
palmer-dabbelt Aug 30, 2023
b8b84a3
riscv: andes: add GPL to readl_fixup() EXPORT_SYMBOL
Jan 25, 2024
678baca
spi: andes: atcspi200: Register the spi interrupt
Nov 23, 2023
eff0449
spi: andes: atcspi200: spi support ads7846 touchscreen
Nov 23, 2023
9f08921
spi: andes: atcspi200: supports quad read write mode
Dec 26, 2023
d7b0b89
rtc: andes: atcrtc100: Use the native Linux IO APIs to read and write…
Mar 20, 2024
fa241aa
rtc: andes: atcrtc100: handle the situation where the size of the day…
Mar 20, 2024
1b88112
rtc: andes: atcrtc100: Support range_min and range_max to extend RTC …
Mar 28, 2024
b57a6d3
drivers: soc: andes: fix cpu_dcache_[wb/inval]_range() failed on 64-b…
Apr 9, 2024
1e42bbc
drivers: i2c: andes: using subsys_initcall (#136) fix bug30592
randolph-lin Dec 26, 2023
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spi: andes: atcspi200: supports quad read write mode
1. Since the SFDP table doesn't define quad page program, a fixup hook
   has been added to enable its support.
2. Currently, the ATCSPI200 supports regular mode read and write, as
   well as quad read and write. Additionally, it utilizes the exec_op
   method to replace the one-transfer approach.

Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Locus Wei-Han Chen authored and charles committed Mar 28, 2024

Verified

This commit was created on GitHub.com and signed with GitHub’s verified signature.
commit 9f08921ce30bc8ab8543bba8c740f8b6bfc50f24
15 changes: 14 additions & 1 deletion drivers/mtd/spi-nor/macronix.c
Original file line number Diff line number Diff line change
@@ -28,6 +28,17 @@ mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
return 0;
}

static void mx25u1635_late_init(struct spi_nor *nor)
{
nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_4_4],
SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);
}

static const struct spi_nor_fixups mx25u1635_fixups = {
.late_init = mx25u1635_late_init,
};

static const struct spi_nor_fixups mx25l25635_fixups = {
.post_bfpt = mx25l25635_post_bfpt_fixups,
};
@@ -101,7 +112,9 @@ static const struct flash_info macronix_nor_parts[] = {
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
{ "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
PARSE_SFDP
.fixups = &mx25u1635_fixups,
},
};

static void macronix_nor_default_init(struct spi_nor *nor)
124 changes: 83 additions & 41 deletions drivers/spi/spi-atcspi200.c
Original file line number Diff line number Diff line change
@@ -49,10 +49,16 @@
#define ATCSPI200_TRANSCTRL_WRTRANCNT_MASK (0x1FF << ATCSPI200_TRANSCTRL_WRTRANCNT_OFFSET)
#define ATCSPI200_TRANSCTRL_RDTRANCNT_OFFSET 0
#define ATCSPI200_TRANSCTRL_RDTRANCNT_MASK (0x1FF << ATCSPI200_TRANSCTRL_RDTRANCNT_OFFSET)
#define CMD_EN (1 << 30)
#define ADDR_EN (1 << 29)
#define DUAL_QUAD(x) (x << 22)
#define DUMMY_CNT(x) ((x - 1) << 9)
#define RDTRAN_CNT(x) ((x == 0) ? 0 : (x - 1) << 0)
#define DUMMY_CNT(x) ((x == 0) ? 0 : (x - 1) << 9)
#define WRTRAN_CNT(x) ((x == 0) ? 0 : (x - 1) << 12)
#define TOKEN_VAl(x) ((x == 0) ? 0 : (1 << 11))
#define TOKEN_EN(x) ((x == 0) ? 0 : (1 << 21))
#define DUAL_QUAD(x) ((x == 0) ? 0 : (x << 22))
#define TRANSMODE(x) ((x == 0) ? 0 : (x << 24))
#define ADDR_FMT(x) ((x == 0) ? 0 : (1 << 28))
#define ADDR_EN(x) ((x == 0) ? 0 : (1 << 29))
#define CMD_EN(x) ((x == 0) ? 0 : (1 << 30))

/* SPI Control Register */
#define ATCSPI200_CTRL_TXFIFORST_MASK (1 << 2)
@@ -91,6 +97,11 @@
#define SPI_INTR_ST 0x3C // SPI Interrupt Status Registe
#define SPI_TIMING 0x40 // SPI Interface timing Register

/* SPI transfer mode */
#define REGULAR_MODE 0x1
#define DUAL_MODE 0x2
#define QUAD_MODE 0x4

struct ts_buf {
u8 cmd;
__be16 data;
@@ -115,6 +126,7 @@ struct atcspi200_spi {
unsigned int mtiming;
int timeout;
spinlock_t lock;
struct mutex mutex_lock;
};

static void atcspi200_spi_write(struct atcspi200_spi *spi, int offset, u32 value)
@@ -268,12 +280,13 @@ static int transfer_data(struct atcspi200_spi *spi, u8 *rx_buf, u8 *tx_buf, int
int num_bytes, rf_cnt;
u8 *dout = tx_buf;
u8 *din = rx_buf;
int timeout = spi->timeout;

num_bytes = (spi->trans_len) % CHUNK_SIZE;
if (num_bytes == 0)
num_bytes = CHUNK_SIZE;

while (num_blks) {
while (num_blks && (timeout--)) {
event = atcspi200_spi_read(spi, SPI_STATUS);
if ((event & ATCSPI200_STATUS_TXEMPTY_OFFSET) && (tx_buf)) {
atcspi200_spi_tx(spi, dout);
@@ -430,28 +443,71 @@ static int atcspi200_spi_transfer_one_message(struct spi_master *master, struct
return 0;
}

static void atcspi200_set_qmode(struct atcspi200_spi *spi, const struct spi_mem_op *op)
static void atcspi200_set_transfer_ctl(struct atcspi200_spi *spi,
const struct spi_mem_op *op)
{
int tc = 0;

tc |= (CMD_EN | ADDR_EN | DUAL_QUAD(2) | ATCSPI200_TRANSMODE_DMYREAD | DUMMY_CNT(4));

/* Set transfer length. */
if (op->cmd.nbytes)
tc |= CMD_EN(op->cmd.nbytes);
if (op->addr.nbytes) {
tc |= ADDR_EN(op->addr.nbytes);
if (op->addr.buswidth > 1)
tc |= ADDR_FMT(1);
}
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN)
tc |= ((spi->trans_len - 1) << ATCSPI200_TRANSCTRL_RDTRANCNT_OFFSET);
else
tc |= ((spi->trans_len - 1) << ATCSPI200_TRANSCTRL_WRTRANCNT_OFFSET);

switch (op->data.buswidth) {
case REGULAR_MODE:
tc |= DUAL_QUAD(0);
break;
case DUAL_MODE:
tc |= DUAL_QUAD(1);
break;
case QUAD_MODE:
tc |= DUAL_QUAD(2);
break;
}
if (op->data.dir == SPI_MEM_DATA_IN) { /* rx */
if (op->dummy.nbytes) {
tc |= ATCSPI200_TRANSMODE_DMYREAD;
if (tc & DUAL_QUAD(2)) {
tc |= DUMMY_CNT(2);
tc |= TOKEN_EN(1);
}
} else {
tc |= ATCSPI200_TRANSMODE_R_ONLY;
}
tc |= RDTRAN_CNT(op->data.nbytes);
} else {
tc |= ATCSPI200_TRANSMODE_W_ONLY;
tc |= WRTRAN_CNT(op->data.nbytes);
}
} else {
tc |= ATCSPI200_TRANSMODE_NONEDATA;
}

/* Set SPI_TRANSCTRL and address register. */
atcspi200_spi_write(spi, SPI_TRANSCTRL, tc);
}

static int atcspi200_spi_setting(struct atcspi200_spi *spi, const struct spi_mem_op *op)
{
/* Set SPI transfer ctl register */
atcspi200_set_transfer_ctl(spi, op);

/* Set SPI address register. */
if (op->addr.nbytes)
atcspi200_spi_write(spi, SPI_ADDR, spi->addr);
atcspi200_spi_write(spi, SPI_ADDR, op->addr.val);

/* Write cmd to start SPI. */
atcspi200_spi_write(spi, SPI_CMD, op->cmd.opcode);

return 0;
}

static int atcspi200_nor_adjust_op_size(struct spi_mem *mem,
struct spi_mem_op *op)
{
op->data.nbytes = min(op->data.nbytes, MAX_TRANSFER_LEN);

return 0;
}

static irqreturn_t andes_spi_irq(int irq, void *dev_id)
@@ -461,21 +517,14 @@ static irqreturn_t andes_spi_irq(int irq, void *dev_id)

static int atcspi200_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
int ret, max_trans_len, data_len, trans_len, num_blks, num_chunks;
int ret;
struct spi_device *atcspi200_spi = mem->spi;
struct atcspi200_spi *spi = spi_master_get_devdata(atcspi200_spi->master);

if (op->cmd.opcode != SPINOR_OP_READ_1_1_4)
return -ENOTSUPP;

mutex_lock(&spi->mutex_lock);
/* Check spi status. */
atcspi200_polling_spiactive(spi);

max_trans_len = spi->max_transfer_length = MAX_TRANSFER_LEN;
data_len = spi->data_len = op->data.nbytes;
num_chunks = DIV_ROUND_UP(data_len, max_trans_len);
spi->addr = op->addr.val;

if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN) {
spi->din = op->data.buf.in;
@@ -485,28 +534,21 @@ static int atcspi200_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *o
spi->din = 0;
}
}
/* set transfer length and data information. */
ret = atcspi200_spi_setting(spi, op);
/* Transfer data */

while (num_chunks--) {
/* set transfer length and data information. */
trans_len = min_t(size_t, data_len, max_trans_len);
spi->trans_len = trans_len;
num_blks = DIV_ROUND_UP(trans_len, CHUNK_SIZE);
atcspi200_set_qmode(spi, op);
/* Transfer data */
data_len = transfer_data(spi, spi->din, spi->dout, num_blks);

if (data_len)
spi->addr += max_trans_len;
transfer_data(spi, spi->din, spi->dout, op->data.nbytes);

ret = atcspi200_spi_stop(spi);
}
ret = atcspi200_spi_stop(spi);
mutex_unlock(&spi->mutex_lock);

return ret;
}

static const struct spi_controller_mem_ops atcspi200_mem_ops = {
.exec_op = atcspi200_exec_mem_op,
.adjust_op_size = atcspi200_nor_adjust_op_size,
};

static int atcspi200_spi_probe(struct platform_device *pdev)
@@ -603,7 +645,7 @@ static int atcspi200_spi_probe(struct platform_device *pdev)

/* Define our master */
master->bus_num = pdev->id;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_QUAD;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_QUAD | SPI_TX_QUAD;
master->dev.of_node = pdev->dev.of_node;
master->num_chipselect = num_cs;
master->transfer_one_message = atcspi200_spi_transfer_one_message;