A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The second layer is the hidden layer and has 100 neurons; the last layer is the output layer with 10 neurons.
The following figure is my block diagram. It takes one image as input at a time, and by modifying the IMAGE in the testbench, different images can be used to obtain test results. There are several registers in the top module, which differ from those provided by the teaching assistant.
The input trigger is used to start computing FC1. When en_compute_FC1 = 1, start to compute the output spike in the hidden layer.
The output trigger is used to start checking the answer of FC1. When en_compute_FC1_finish = 1, start to check the answer of the output spike in the hidden layer.
The input trigger is used to start computing FC2. When en_compute_FC2 = 1, start to compute the output spike in the output layer.
The output trigger is used to start checking the answer of FC2. When en_compute_FC2_finish = 1, start to check the answer of the output spike in the output layer.
The following figure is the FSM of the whole system. The inside controllers of FC1/FC2 are the same. The timestep of each image is the most important part of the whole system. Because we need to use the membranes of the previous timestep, so we need to save them for each timestep. I used several counters to count the timesteps and the address of SRAM A and SRAM B.
The total timesteps I chose is 35. First, divide the timesteps into 0 and 1-34. In the simulation of the software, in the first layer, Vth = 68, and in the second layer, Vth = 91. I use the following formula to calculate mem:
In timestep 1 to 34, I need to use the membranes after resetting from the previous timestep. So, in timestep 0, I first output and record the reset membranes in the top module. When I reach timestep 1, I then input these values.
