IP Core

Author: yjlcoder

MipsCPU.xise

@@ -52,19 +52,19 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="mips.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="insRom.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="cpu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="cpu_tb.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
@@ -74,9 +74,30 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="ram.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
+    <file xil_pn:name="control.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/instMem_ip.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/clk_ip.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+    </file>
+    <file xil_pn:name="implemention.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/instMem_ip.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/clk_ip.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+    </file>
   </files>
 
   <properties>
@@ -263,6 +284,7 @@
     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
     <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -338,6 +360,7 @@
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-PE Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target UCF File Name" xil_pn:value="implemention.ucf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
@@ -394,7 +417,9 @@
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
 
-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/cpu" xil_pn:name="implemention.ucf"/>
+  </bindings>
 
   <libraries/>
 

control.v

@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:39:48 12/11/2015 
+// Design Name: 
+// Module Name:    control 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module control(
+    /*
+    * control_output[5] -> writeback 
+    * control_output[4] -> memory
+    * control_output[3] -> execute
+    * control_output[2] -> insDecode
+    * control_output[1] -> insFetch
+    * control_output[0] -> PC 
+    */ 
+    input rst,
+    input insDecode_pause,
+    input execute_pause,
+    output reg[5:0] control_output
+    );
+
+    always @ (*) begin
+        if(rst == 1) begin
+            control_output <= 0;
+        end else if(execute_pause == 1)
+            control_output <= 6'b001111;
+        else if(insDecode_pause == 1)
+            control_output <= 6'b000111;
+    end
+
+endmodule

cpu.v

@@ -33,11 +33,19 @@ module cpu(
     wire[31:0] ram_data_output;
     wire[3:0] ram_select_output;
     wire ram_write_enabler;
+
+    wire clk0;
+
+    clk_ip clk_ip0(
+        .CLK_IN1(clk),
+        .CLK_OUT1(clk0)
+    );
+
     //wire ram_enabler;
 
     mips mips0(
         .rst(rst), 
-        .clk(clk),
+        .clk(clk0),
         .ins_input(inst),
         .addr_output(instAddr),
         .enabler_output(enabler),
@@ -50,14 +58,14 @@ module cpu(
         .ram_enabler(ram_enabler)
     );
 
-    instRom instRom0(
-        .enabler(enabler),
-        .addr(instAddr),
-        .inst(inst)
+    instMem_ip instRom0(
+        //.enabler(enabler),
+        .a(instAddr[11:2]),
+        .spo(inst)
     );
 
     ram ram0(
-        .clk(clk),
+        .clk(clk0),
         .enabler(ram_enabler),
         .write_enabler(ram_write_enabler),
         .addr(ram_addr_output),

cpu_tb.v

@@ -27,11 +27,13 @@ module cpu_tb;
 	// Inputs
 	reg rst;
 	reg clk;
+    wire ram_enabler;
 
 	// Instantiate the Unit Under Test (UUT)
 	cpu uut (
 		.rst(rst), 
-		.clk(clk)
+		.clk(clk),
+        .ram_enabler(ram_enabler)
 	);
 
 	initial begin

execute.v

@@ -54,7 +54,9 @@ module execute(
     input wire[31:0] insDecode2execute_ins,
     output wire[7:0] aluop_output,
     output wire[31:0] mem_addr_output,
-    output wire[31:0] regOp2_output
+    output wire[31:0] regOp2_output,
+
+    output execute_pause_output
     );
 
     reg [31:0] opOut;
@@ -95,6 +97,8 @@ module execute(
 
     assign regOp2_output = regOp2;
 
+    assign execute_pause_output = 0;
+
     always @ (*) begin
         if (rst == 1'b1) begin
             arch_answer <= 0;

execute2memory.v

@@ -42,7 +42,9 @@ module execute2memory(
     input wire[31:0] regOp2,
     output reg[7:0] aluop_output,
     output reg[31:0] mem_addr_output,
-    output reg[31:0] regOp2_output 
+    output reg[31:0] regOp2_output,
+
+    input wire[5:0] control
     );
 
     always @ (posedge clk) begin
@@ -53,7 +55,7 @@ module execute2memory(
             execute2memory_HILO_enabler <= 0;
             execute2memory_HILO_HI <= 0;
             execute2memory_HILO_LO <= 0;
-        end else begin
+        end else if(control[3] == 0) begin
             dest_addr_output <= dest_addr;
             write_or_not_output <= write_or_not;
             wdata_output <= wdata;