arm_biquad_cascade_df1_32x64_q31: asrl(val, -shift) -> lsll(val, shift) #7
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…t) (ARM-software#265) This code was using asrl with an intentionally negative value. GCC 14 doesn't turn that into a left shift, instead it produces 0 for the result. Use lsll instead to get the desired result. Signed-off-by: Keith Packard <keithp@keithp.com> (cherry picked from commit b7a49ac)
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This patch has been accepted upstream ARM-software/CMSIS-DSP#265. The module PR, zephyrproject-rtos/cmsis-dsp#7 is pending review. Signed-off-by: Keith Packard <keithp@keithp.com>
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This patch has been accepted upstream ARM-software/CMSIS-DSP#265. The module PR, zephyrproject-rtos/cmsis-dsp#7 is pending review. Signed-off-by: Keith Packard <keithp@keithp.com>
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This patch has been accepted upstream ARM-software/CMSIS-DSP#265 and into the Zephyr module zephyrproject-rtos/cmsis-dsp#7 This PR is ready for review and merging. Signed-off-by: Keith Packard <keithp@keithp.com>
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This patch has been accepted upstream ARM-software/CMSIS-DSP#265 and into the Zephyr module zephyrproject-rtos/cmsis-dsp#7 This PR is ready for review and merging. Signed-off-by: Keith Packard <keithp@keithp.com>
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This patch has been accepted upstream ARM-software/CMSIS-DSP#265 and into the Zephyr module zephyrproject-rtos/cmsis-dsp#7 This PR is ready for review and merging. Signed-off-by: Keith Packard <keithp@keithp.com>
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This code was using asrl with an intentionally negative value. GCC 14 doesn't turn that into a left shift, instead it produces 0 for the result.
Use lsll instead to get the desired result.
(cherry picked from commit b7a49ac)
Upstream PR: ARM-software#265 (closed)