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@alpsayin alpsayin commented Mar 3, 2025

Tested on a SiFive-FE310G variant with zephyr-sdk 0.16's riscv32-zephyr-gdb

@alpsayin alpsayin force-pushed the zephyr-20220611-riscv32 branch from 457ad09 to ffc6276 Compare March 3, 2025 15:08
alpsayin added 3 commits March 3, 2025 15:08
Tested on a SiFive-FE310G variant with zephyr-sdk 0.16's riscv32-zephyr-gdb

Signed-off-by: Alp Sayin <alpsayin@gmail.com>
Debug logs left here make it easier to trace openocd/zephyr's unwrapping
of the riscv stacks. And could be used for extending support for riscv64.

Signed-off-by: Alp Sayin <alpsayin@gmail.com>
Makes more sense to print thread IDs as hex since they're not just IDs,
they're thread structs' addresses.

Signed-off-by: Alp Sayin <alpsayin@gmail.com>
@alpsayin alpsayin force-pushed the zephyr-20220611-riscv32 branch from ffc6276 to 30ba6b3 Compare March 3, 2025 15:08
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