arch: arm: aarch32: add Kconfig for arm cortex-m that implements a cache

The Cache is an optional configuration of both the ARM Cortex-M7 and Cortex-M55. Previously, it was just checking that it was just an M7 rather than knowing that the CPU actually was built with the cache. Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
zephyrproject-rtos · Apr 14, 2022 · c5b5928 · c5b5928
1 parent f1b0b45
commit c5b5928
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Showing 14 changed files with 29 additions and 3 deletions.
diff --git a/arch/arm/core/aarch32/Kconfig b/arch/arm/core/aarch32/Kconfig
@@ -14,7 +14,7 @@ config CPU_CORTEX_M
 	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
 	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
 	select ARCH_HAS_USERSPACE if ARM_MPU
-	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M7
+	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_CORTEX_M_HAS_CACHE
 	select ARCH_HAS_RAMFUNC_SUPPORT
 	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
 	select SWAP_NONATOMIC

diff --git a/arch/arm/core/aarch32/cortex_m/Kconfig b/arch/arm/core/aarch32/cortex_m/Kconfig
@@ -86,6 +86,13 @@ config CPU_CORTEX_M_HAS_SYSTICK
 	help
 	  This option is enabled when the CPU implements the SysTick timer.
 
+config CPU_CORTEX_M_HAS_CACHE
+	bool
+	depends on CPU_CORTEX_M7 || CPU_CORTEX_M55
+	help
+	  This option signifies that the CPU implements Data and Instruction
+	  Cache
+
 config CPU_CORTEX_M_HAS_DWT
 	bool
 	depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1

diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/aarch32/cortex_m/scb.c
@@ -108,7 +108,7 @@ void z_arm_init_arch_hw_at_boot(void)
 		NVIC->ICPR[i] = 0xFFFFFFFF;
 	}
 
-#if defined(CONFIG_CPU_CORTEX_M7)
+#if defined(CONFIG_CPU_CORTEX_M_HAS_CACHE)
 	/* Reset D-Cache settings. If the D-Cache was enabled,
 	 * SCB_DisableDCache() takes care of cleaning and invalidating it.
 	 * If it was already disabled, just call SCB_InvalidateDCache() to
@@ -121,7 +121,7 @@ void z_arm_init_arch_hw_at_boot(void)
 	}
 	/* Reset I-Cache settings. */
 	SCB_DisableICache();
-#endif /* CONFIG_CPU_CORTEX_M7 */
+#endif /* CONFIG_CPU_CORTEX_M_HAS_CACHE */
 
 	/* Restore Interrupts */
 	__enable_irq();

diff --git a/soc/arm/arm/mps3/Kconfig.soc b/soc/arm/arm/mps3/Kconfig.soc
@@ -8,6 +8,7 @@ choice
 config SOC_MPS3_AN547
 	bool "Arm Cortex-M55 SSE-300 on MPS3 (AN547)"
 	select CPU_CORTEX_M55
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU

diff --git a/soc/arm/arm/mps3/soc.h b/soc/arm/arm/mps3/soc.h
@@ -15,6 +15,8 @@
 #define __DSP_PRESENT             1U        /* DSP extension present */
 #define __MVE_PRESENT             1U        /* MVE extensions present */
 #define __MVE_FP                  1U        /* MVE floating point present */
+#define __ICACHE_PRESENT          1U        /* ICACHE present */
+#define __DCACHE_PRESENT          1U        /* DCACHE present */
 #endif
 
 

diff --git a/soc/arm/atmel_sam/same70/Kconfig.series b/soc/arm/atmel_sam/same70/Kconfig.series
@@ -10,6 +10,7 @@ config SOC_SERIES_SAME70
 	select SOC_FAMILY_SAM
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_CORTEX_M_HAS_DWT
+	select CPU_CORTEX_M_HAS_CACHE
 	select ASF
 	select XIP
 	select CPU_HAS_ARM_MPU

diff --git a/soc/arm/atmel_sam/samv71/Kconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.series
@@ -10,6 +10,7 @@ config SOC_SERIES_SAMV71
 	select CPU_CORTEX_M7
 	select SOC_FAMILY_SAM
 	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 	select ASF
 	select XIP

diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.series
@@ -7,6 +7,7 @@ config SOC_SERIES_VALKYRIE
 	bool "Broadcom Valkyrie Series"
 	select ARM
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select SOC_FAMILY_BCMVK
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_HAS_ARM_MPU

diff --git a/soc/arm/bcm_vk/viper/Kconfig.soc b/soc/arm/bcm_vk/viper/Kconfig.soc
@@ -8,6 +8,7 @@ depends on SOC_SERIES_VIPER
 config SOC_BCM58402_M7
 	bool "Broadcom BCM58402 M7"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_HAS_ARM_MPU
 	select CORTEX_M_SYSTICK

diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series
@@ -7,6 +7,7 @@ config SOC_SERIES_IMX8ML_M7
 	bool "i.MX8ML M7 Core Series"
 	select ARM
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select SOC_FAMILY_IMX
 	select CPU_HAS_FPU
 	select INIT_VIDEO_PLL

diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc
@@ -277,6 +277,7 @@ config SOC_MIMXRT1064
 config SOC_MIMXRT1176_CM7
 	bool "SOC_MIMXRT1176_CM7"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_SERIES_IMX_RT11XX
 	select HAS_MCUX_CACHE
@@ -337,6 +338,7 @@ config SOC_MIMXRT1176_CM4
 config SOC_MIMXRT1166_CM7
 	bool "SOC_MIMXRT1166_CM7"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_SERIES_IMX_RT11XX
 	select HAS_MCUX_CACHE
@@ -563,6 +565,7 @@ config SOC_PART_NUMBER_IMX_RT
 config SOC_SERIES_IMX_RT10XX
 	bool "i.MX RT 10XX Series"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 
 config SOC_SERIES_IMX_RT11XX

diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.series b/soc/arm/nxp_kinetis/kv5x/Kconfig.series
@@ -7,6 +7,7 @@ config SOC_SERIES_KINETIS_KV5X
 	bool "Kinetis KV5x Series MCU"
 	select ARM
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_FAMILY_KINETIS
 	select CPU_HAS_ARM_MPU

diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.series b/soc/arm/st_stm32/stm32f7/Kconfig.series
@@ -7,6 +7,7 @@ config SOC_SERIES_STM32F7X
 	bool "STM32F7x Series MCU"
 	select ARM
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select SOC_FAMILY_STM32

diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.soc b/soc/arm/st_stm32/stm32h7/Kconfig.soc
@@ -12,16 +12,19 @@ choice
 config SOC_STM32H723XX
 	bool "STM32H723XX"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 
 config SOC_STM32H725XX
 	bool "STM32H725XX"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 
 config SOC_STM32H735XX
 	bool "STM32H735XX"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 
 config SOC_STM32H743XX
@@ -32,14 +35,17 @@ config SOC_STM32H743XX
 config SOC_STM32H745XX
 	bool "STM32H745XX"
 	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE if CPU_CORTEX_M7
 
 config SOC_STM32H747XX
 	bool "STM32H747XX"
 	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE if CPU_CORTEX_M7
 
 config SOC_STM32H750XX
 	bool "STM32H750XX"
 	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_CACHE
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 
 config SOC_STM32H753XX