i.MX RT1170 / 1176 - enet1g issue with dual core build

[ehughes]

I believe there is an issue with the gigabit ethernet driver for the RT1170 EVK when the 2nd core is enabled.

1.) Control Experiment

I compiled the DHCPv4_client using the extra overlay "-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay" mentioning on the board doc page. This ran successfully. I could see the board get a DHCP lease and I could ping, etc.

2.) Dual Core Setup

I added the code from the DHCP sample to the "OpenAmp" sample. This is the primary project to should dual core setup w/ the RT1170. It was build w/ sysbuild:

west build -b mimxrt1170_evk@A/mimxrt1176/cm7 --sysbuild --pristine -- -D"EXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay"

When the 2nd core is started, the network inerface will never come up. The driver will report 1 log message:

[00:00:00.061,000] <inf> eth_nxp_enet_mac: Link is down

before the application starts.

If I disabled "CONFIG_SECOND_CORE_MCUX", I can get network activity.

I saw this symbol was used in a few places in imxrt11xx/soc.c

I original thought it had to do with this lines:

#ifdef CONFIG_INIT_ENET_PLL
	CLOCK_InitSysPll1(&sysPll1Config);
#else
#ifndef CONFIG_SECOND_CORE_MCUX
	/* Bypass Sys Pll1. */
	CLOCK_SetPllBypass(kCLOCK_PllSys1, true);

	/* DeInit Sys Pll1. */
	CLOCK_DeinitSysPll1();
#endif
#endif

However, if I short circuited the startup of the 2nd core (but left the PLL settings), the network interface came up.

static int second_core_boot(void)
{
//short circuit
return;

	/* Kick CM4 core out of reset */
	SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK;
	SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK;
#if DUAL_CORE_MU_ENABLED
	/* Wait for the secondary core to start up and set boot flag in
	 * imxrt_init
	 */
	while (MU_GetFlags(MU_BASE) != BOOT_FLAG) {
		/* Wait for secondary core to set flag */
	}
#endif
	return 0;
}

Any ideas of where do look next? The M4 code for the openamp sample is pretty simple. It wasn't doing anything obvious with the networking interface in the application code.

My best guess is that the m4 is using the same soc.c and the clocks/pinmux maybe getting modified by the m4 core.

[DerekSnell]

Hi @ehughes ,
Yes, both cores share the soc.c file, and both execute imxrt_init() and clock_init(). It sounds like there is some contention when the M4 core initializes. My guess is in clock_init().

You could debug by modifying soc.c and use the Kconfigs CONFIG_SOC_MIMXRT1176_CM4 and CONFIG_SOC_MIMXRT1176_CM7 to narrow down the conflict.

Please let us know what you find. Thanks