AArch64 / Cortex-A port improvements / TODO

[carlocaione]

#20263 introduced the basic support for AArch64 / Cortex-A.

This issue is used to track the TODO / WiP work.

WiP:

• MMU support: Add Cortex-A53 (ARMv8, AArch64) support #20263 (comment) and arch: arm64: ARM64 port not working on real target #22410 (@Abhishek-brcm) [ARMv8-A MMU support #22446]
• Support for Xilinx ZynqMP APU (@carlocaione) [soc: arm64: Add support for Xilinx ZynqMP APU #22418]
• Rework interrupt handling (remove cascade IRQ controller) (@stephanosio) [Refactor ARM interrupt system (Cortex-A & Cortex-R) #22718]
• Support SMP and switch to arch_switch() (@carlocaione [[RFC] Use new-style arch_switch instead of arch_swap #22877]

TODO:

• Merge shared code between Cortex-R / Cortex-A
• Support GICv3 drivers: add GIC V3 driver #24850 (@sandeepbrcm )
• Do not update sp with each STP instruction (Add Cortex-A53 (ARMv8, AArch64) support #20263 (comment))
• User-mode Support with EL0

[carlocaione]

tagging interested / relevant people: @stephanosio @Abhishek-brcm @sandeepbrcm @timork @Mani-Sadhasivam @andrewboie @Jojjec1 @ioannisg @ehudmarvell @vladimir-podbrezsky

Feel free to add / modify the list.

[carlocaione]

This is outdated. Closing for now.

[JohnCarterGonzalez]

Am I correct in assuming that because this issue is closed it means that Zephyr has Cortex A family support?

[carlocaione]

Am I correct in assuming that because this issue is closed it means that Zephyr has Cortex A family support?

yes