ARM Cortex-M7: add support for non-cacheable RAM region #2927
Description
Reported by Piotr Mienkowski:
ARM Cortex-M7 integrates instruction and data caches. ARM CMSIS provides cache clean and invalidate operations however not all cache coherence issues can be solved using cache maintenance operations. At times the only solution is using the so called non-cacheable RAM memory region. That requires dedicated RTOS support.
In Zephyr we need to add a new non-loadable linker section called e.g. data_nocache and provide a function to configure this region in MPU as shared.
ARM MPU module puts some limits on the size and start address of such region. The region size has to be the power of two with the minimum size being 32 bytes. The region start address has to be aligned with the size of the region, e.g. a 64KB region must be aligned on a multiple of 64KB, it can start at e.g. 0x00010000 or 0x00020000.
Since the region alignment requirements are quite strong the best location for such a section would be likely at the beginning or end of RAM. Also, due to the fact that alignment requirements are changing together with size of the region it may be difficult or impossible to write a linker script which automatically configures the section layout based on the size of the symbols. In such case the region's size needs to be defined by a Kconfig option.
(Imported from Jira ZEP-1455)