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Intel_adsp_ace1x: Meteorlake board upstream #46323

Merged
merged 21 commits into from
Jul 6, 2022
Merged

Intel_adsp_ace1x: Meteorlake board upstream #46323

merged 21 commits into from
Jul 6, 2022

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aborisovich
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@aborisovich aborisovich commented Jun 6, 2022 •
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Publishing new ACE1X SoC Meteorlake board.
This set of commits is related to board and hardware definitions.
Note for reviewers:

  • This PR is a "first half" of the upstream process. It contains zephyr board, soc and hardware characteristics.
  • Second part will be published later - it will contain drivers code.

@aborisovich aborisovich added the platform: Intel ADSP Intel Audio platforms label Jun 6, 2022
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mwasko commented Jun 7, 2022

@aborisovich there is a lot of commits that require squash in this PR. All the renames, remove commits are irrelevant information on the upstream. Similar apply to some minor changes related to board files and ACE 1.x SoC.

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mwasko previously requested changes Jun 7, 2022
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Please clean up commits and squash irrelevant ones.

@aborisovich aborisovich force-pushed the mtl-board-upstream branch from 901fa96 to a292717 Compare June 9, 2022 07:07
@zephyrbot zephyrbot added area: Xtensa Xtensa Architecture area: Audio labels Jun 9, 2022
mwasko
mwasko reviewed Jun 9, 2022
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@aborisovich will the Meteorlake board compile without the configuration file? If not then it should be part of the Meteorlake board commit.

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kv2019i requested changes Jun 9, 2022
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Thanks @aborisovich ! Overall looks good. Aside a few minor issues, bigger issues are shared definitions with cAVSxx (either clean up the old one, or use common header for common parts), and what we do with xtensa/config.

soc/xtensa/intel_adsp/ace_v1x/Kconfig.soc Outdated Show resolved Hide resolved
soc/xtensa/intel_adsp/ace_v1x/cavs-ipc-regs.h Outdated Show resolved Hide resolved
soc/xtensa/intel_adsp/ace_v1x/cavs-ipc-regs.h Outdated Show resolved Hide resolved
soc/xtensa/intel_adsp/ace_v1x/cavs-ipc-regs.h Outdated Show resolved Hide resolved
soc/xtensa/intel_adsp/ace_v1x/multiprocessing.c Outdated Show resolved Hide resolved
soc/xtensa/intel_adsp/ace_v1x/xtensa/config/core-isa.h Outdated Show resolved Hide resolved
@aborisovich aborisovich force-pushed the mtl-board-upstream branch from a292717 to 2da3178 Compare June 9, 2022 20:01
@marc-hb marc-hb removed their request for review June 10, 2022 01:31
@aborisovich aborisovich force-pushed the mtl-board-upstream branch 3 times, most recently from 3dd89eb to f1c8b79 Compare June 10, 2022 10:02
@aborisovich aborisovich marked this pull request as ready for review June 10, 2022 10:02
@aborisovich aborisovich requested a review from galak as a code owner June 10, 2022 10:02
nashif and others added 17 commits July 6, 2022 18:13
@nashif @abonislawski
drivers: dma: Add gpdma derivative of dw dma for ace
2970fe1 
This will add ace compatible DMA driver.

Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
@nashif @mwasko
@kleszczy @rfredzim @enjiamai @tmleman @abonislawski @serhiy-katsyuba-intel
intel_adsp: add a new series to support Meteorlake
4b2c617 
Meteorlake support as part of the Intel ADSP family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
@nashif @mwasko @kleszczy
intel_adsp: add the board definition for the Meteorlake
f112fd9 
Board definition for the meteorlake platform.
Enable intel_adsp_ace15_mtpm in the sof sample.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
@rfredzim
ace: multiprocessing: enable secondary core boot through ROM
b12e51f 
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
@rfredzim @tmleman
ace: multiprocessing: add polling for core powered up confirmation
bf9ee7f 
Poll for CPA bit by which HW confirms that the core has been powered up.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
dts: align CONFIG's with ace hardware
b4c8580 
Align CONFIG_HEAP_MEM_POOL_SIZE & CONFIG_DAI with ace hardware.

Signed-off-by: Arsen Eloglian <ArsenX.Eloglian@intel.com>
@tmleman
soc: ace_v1x: soc_adsp_halt_cpu implementation
24a1a9e 
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@tmleman
soc: ace_v1x: pm_state_set implementation
a41c658 
This patch implements pm_state_set function for ACE platforms.

This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@tmleman
soc: ace_v1x: pm_state_exit_post_ops implementation
bbe2241 
Implementation of the function used during the exit from the lower power
states.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@nashif
soc: ace1.x: use common code
315311b 
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
soc: ace1x: provided register names to addresses
5817b01 
Provided register names to hardcoded addresses in ace_v1x-regs
header.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
intel_adsp: Unify cavs and ace timers
e6aa9a1 
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
soc: ace: Move power management to its own file
4ebd1a1 
Move power management hooks to its own C file.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
soc: ace: Organizing include headers
494a857 
Properly prefixing some include files with "zephyr", also organizing
the order they are included.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
soc: adsp: sram: Assorted cosmetic fixes
8073b1c 
General code style fixes.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
manifest: hal_xtensa: updates to new ace family definitions
21e23d6 
Updated hal_xtensa module with new xtensa definitions
for intel_adsp_ace1x soc family.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
soc: intel_adsp: reading HP SRAM banks count for ACE1X from Devicetree
aa87a95 
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
@aborisovich aborisovich force-pushed the mtl-board-upstream branch from c182472 to d83138e Compare July 6, 2022 16:13
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Push update:
As @dcpleung noticed IMR driver source file was not compiled and had errors when enabled.
Removed IMR driver from this PR.

@ceolin ceolin requested a review from dcpleung July 6, 2022 16:18
soc: intel_adsp: added casting for C++ compiler in soc.h
a132e5d 
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
@aborisovich aborisovich force-pushed the mtl-board-upstream branch from d83138e to a132e5d Compare July 6, 2022 18:05
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nashif commented Jul 6, 2022

net test failure unrelated,

@nashif nashif merged commit e0b1d81 into zephyrproject-rtos:main Jul 6, 2022
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marc-hb commented Jul 7, 2022 •
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Most SOF testing is failing today with Zephyr commit 2d54229 example: https://sof-ci.01.org/linuxpr/PR3742/build343/devicetest/

(non-Zephyr tests are fine)

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marc-hb commented Jul 7, 2022 •
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My bad, the last successful SOF daily testing (test run 13760 yesterday) was with commit e0b1d81 which happens to be the last commit of this series. Sorry for the noise!

The current suspect is now @ceolin 's "simplify PM" 158a870...

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marc-hb commented Jul 8, 2022

and the winner is....

Apologies to @ceolin , I would have never expected a one-line CMake change to have such a devastating run-time impact so the only other actual xtensa code change was the only (and wrong) suspect left.

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area: Audio area: Boards area: Build System area: Devicetree Binding PR modifies or adds a Device Tree binding area: Devicetree area: DMA Direct Memory Access area: Interrupt Controller area: Samples Samples area: Timer Timer area: Xtensa Xtensa Architecture manifest manifest-hal_xtensa manifest-sof platform: Intel ADSP Intel Audio platforms
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