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@rgundi rgundi commented Mar 28, 2018

This patchset brings Zephyr support to Intel S1000. The GPIO, UART, I2C, DMA and I2S drivers along with interrupt controllers are currently supported.

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codecov-io commented Mar 28, 2018

Codecov Report

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@SavinayDharmappa SavinayDharmappa self-requested a review March 29, 2018 06:20
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Please combine these into a single commit. The older shell script-based way of working is not supported anymore.

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Done.

@rgundi rgundi force-pushed the S1000_migrate branch 2 times, most recently from d8acde8 to 83e51eb Compare April 3, 2018 14:38
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Some random whining but nothing that I think should block merge by itself.

I do note the lack of asm2 integration. Was that not working out with xcc? Any particular problems?

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Why not just use main() for this thread? This just looks like a waste of memory to me.

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This is the way it has been done for all the tests for peripherals in S1000. Just keeps "main" clean and it's easier to add and remove tests (via CMakeLists.txt).

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This patch should be a test in the USB subsystem, or else a sample. I don't see anything board-specific here at all. Also needs a YAML descriptor and ztest integration if it lives in tests/.

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YAML descriptor and ztest integration will happen in a future patchset.

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Isn't this missing a ton of stuff? I'm seeing multiple drivers in this pull requests that aren't represented here in the hardware description.

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This is not fully complete. We haven't finished migrating all drivers to DTS. This will also happen separately driver by driver in future patchsets.

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This was floating around a while back, and I didn't understand it then either. Which component on Xtensa needs "__start" to be identical with the reset vector? I mean, this isn't wrong. I just don't see why we should care what the arch names its boot vectors.

Is the problem that some flashing tool is assuming that ResetVector and the ELF start vector are the same or something?

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Well.. on S1000, the "make debug" and "make flash" commands download the ELF file on to the beginning of SRAM (address is 0xBE000000). Upon Power on, ROM code gets executed and jumps to SRAM location 0xBE000000. So, the first piece of code that we want to be executed in SRAM needs to be placed at 0xBE000000. Since there is already a different __start in the Xtensa code, that was getting placed at that location thereby causing issues. Hence _ResetVector had to be renamed to __start to ensure it gets included in the right area.

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FWIW: it might be a good idea to split the initialization code like this into a macro library and a per-SoC or per-board implementation. This stuff is always going to be very closely tied to the behavior of whatever bootloader coexists with Zephyr, which is going to be vendor-specific. Note that esp32 doesn't use this at all and relies on its own startup code.

Obviously we want to identify the root cause here too. I'm just saying that this kind of "hack" is going to happen again and again as this code gets applied to more hardware. Making the change this way doesn't scale, even if it was perfectly understood.

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I understand your point but i am unsure how to implement it. Can we take this up later?

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Three-letter struct names are likely to collide and don't belong in drivers. Maybe "i2s_cavs_ssp" instead?

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sure. will make the change.

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More broadly: why is this stuff in a header at all? It defines internal data that is only used by or included in one other file, and exposes no APIs for use by other parts of the system. Just put this in the C file.

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This is more of a personal choice, i feel. I wanted to keep some things in the header file to keep the size of the source file reasonable. Also, i wasn't sure if the things that i put in the header file would not be used anywhere else (except the corresponding .c). That said, i can merge the .c an .h files if you insist.

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Style; doing this with a struct literal allows the compiler to generate better code and is more readable:

blk_cfg = {
   .block_size = blk_size,
   .source_address = (u32_t)src,
   .dest_address = (u32_t)dst,
}

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sure. will make the change.

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So... start_dma() doesn't enable DMA? Is that racy? Seems like this needs a comment explaining why this is OK. Maybe "start_dma()" should be renamed "setup_dma()"?

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Well.. here the DMA is controlled by the peripheral. So, even if the DMA starts, unless the peripheral enables the DMA, the DMA will not complete. I can put in a comment there.

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Any reason you can't use a k_queue for this? Among other things, I don't see any synchronization of the I2C API here, and a k_queue would give you that for free.

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Guess a k_queue should work here. I don't need any synchronization though. Will give the struct a try and see if things work fine.

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Will anything need to be done here in the future? None of these cases actually perform any operation.

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I initially kept it thinking i may need it for something in future. Haven't used it so far and i don't think i need it anymore. Will remove it. Will reintroduce it in future, if needed.

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Same here.

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will remove this too.

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Please check if channel is within bounds before taking a pointer to the chan array.

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ok.

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Same here.

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ok

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Is this port in particular capable of SMP? If so, we might want to copy the DMA callbacks to local variables before looping through blocks/tfrs.

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Currently this port doesn't have SMP but we may need to support it in future. DMA callbacks are already copied to local variables. Can you let me know what is not copied here?

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With the embedded structs here, will having a boolean in the middle create a unnecessary hole due to alignment?

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Well, not sure if a hole is created here. What is the size of bool in zephyr?

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lpereira commented Apr 3, 2018

I've checked most of these patches already, and there are just a few minor points that I'd like to have fixed before merging this.

BTW, thanks for using DT in an Xtensa port.

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The copy-paste between this file and cmake/compiler/gcc.cmake must be resolved.

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I would recommend organizing this as a "gcc-like" toolchain, so having COMPILER set to gcc, and modifying gcc.cmake to be generic enough to support xcc.

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Agree there are similarities between xcc.cmake and gcc.cmake but there are some differences as well. I prefer taking this up later. Let me know if you agree

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No, the code must be maintainable before it goes into master.

Or else the technical debt is pushed to the next contributor to gcc.cmake, instead of where it rightly belongs.

I am aware there are differences, gcc.cmake must be made generic enough to not require the changes made.

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ok. i have come up with something. Please review once i push the changes.

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This toplevel CMakeLists.txt file should not be aware of the toolchain used.

Perhaps, it would be possible to do:

set(OPTIMIZE_FOR_SIZE_FLAG "-O0")

in the toolchain file.

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Agreed.

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Can it be explained why (AFAICT) the other xtensa toolchains did not require this flag, but this toolchain does?

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The XCC toolchain is derived from an older version of gcc and it does not understand "anonymous structs/unions". Guess it still follows the C99 standard. This flag enables that capability.

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This should also be moved to the toolchain build script.

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should i employ a method similar to the one adopted for OPTIMIZE_FOR_SIZE_FLAG flag? i.e. define a new flag, something like FMS_EXTENSIONS in toolchain build script and then include it under zephyr_compile_options in the toplevel CMakeLists.txt.
Another option is to use zephyr_cc_option directly. It will fail for gcc but work for xcc. Let me know your thoughts.

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Hi, I don't think -fms-extensions will fail for gcc actually.

I believe the cleanest solution will be to do

list(APPEND TOOLCHAIN_C_FLAGS -fms-extensions)

from the xcc toolchain build script.

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Well.. that was my preferred way as well in the beginning when i started providing this support. It just doesn't work. It just doesn't seem to take effect at all. That's the reason why i modified the toplevel CMakeLists.txt.

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Right, so the reason TOOLCHAIN_C_FLAGS is taking effect on 'arm', but not on 'xtensa' is that arm is doing

zephyr_compile_options(
${TOOLCHAIN_C_FLAGS}
)

I suspect that this is undesirable, the toplevel CMakeLists.txt should be doing

zephyr_compile_options(
${TOOLCHAIN_C_FLAGS}
)

so that it is not architecture-dependent whether toolchain flags are used or not.

Anyway, for this particular PR we need to get rid of

+if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "xcc")

in the toplevel CMakeLists.txt file.

This can be done by copying what 'arm' is doing, and executing

zephyr_compile_options(${TOOLCHAIN_C_FLAGS})

in arch/xtensa/CMakeLists.txt

or by adding TOOLCHAIN_C_FLAGS in the toplevel CMakeLists.txt and removing it from arch/{arm,posix}.

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Thanks for the info. I have modified the toplevel CMakeLists.txt and it is working fine.

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Does the toolchain not support this flag?
Or does it use a different flag under another name?

If it is not supported then I would think the if statement was not necessary because
zephyr_ld_options is supposed to test if a flag is supported by the toolchain and omit it if not.

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xcc does not support this flag.

I know that zephyr_ld_options is supposed to test and omit a flag if it is not supported but i saw a few failures initially and was not really sure of the impact. I had then decided to omit it for XCC. Will revert this change now.

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It should be possible to omit the if statement.

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ok

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What the CMake code was originally expressing here was correct.

If the user has enabled STACK_CANARIES, but the toolchain does not support -fstack-protector-all, then the build system should not silently drop the protection.

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ok. Will revert it. Thanks for the explanation.

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It should be possible to omit the if statement.

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ok

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The title underline must be at least as long as the title, so add some more #######. Also, spelling should be Intel

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processor chip

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add a blank line before this sublist

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add a blank line before this sublist too

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blank line before this sublist (and fix the occurances below too)

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Saying "We use" is an unexpected shift. Maybe instead, say, "We recommend using" here.

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Delete the "please":

Connect the J8 header and UART chip as shown below:

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Instead:

Use ``minicom`` or another terminal emulator to monitor the UART data
by following these steps:

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Instead:

For debugging, you can use a flyswatter2 to connect to the S1000 CRB.

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If you intended for these links to show up in the generated output, add this directive before them:

.. target-notes::

and a blank line.

@SavinayDharmappa SavinayDharmappa requested a review from galak April 5, 2018 06:31
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@galak could you review dts support for xtensa ?

rgundi and others added 20 commits April 26, 2018 12:06
__start is deemed the entry point for all architectures in Zephyr.
Accordingly, Xtensa code had to be modified a bit to fall in line
with this convention.

Change-Id: If3ed344721c9f2735378b866662a68d8d5795324
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.

Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 makes use of DesignWare IP for I2C.

Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CAVS interrupt logic is an intel IP that combines several sources of
interrupt into one line that is then routed to the parent controller.
CAVS stands for "connected Audio, Voice and Speech". This IP supports
4 lines which can have a max of 32 interrupts each.

Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This interrupt controller is a designware IP that combines several
sources of interrupt into one line that is then routed to the parent
controller.

This implementation supports only the regular irqs with no support
for priority filtering and vectored interrupts. Firqs are also not
supported.

Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.

Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset carries out basic tests on the features supported
on intel_s1000. Currently, Interrupt mechanism, GPIO handling, I2C
communication and UART prints are illustrated.

Change-Id: I7ea03b5085b7fa8d29635c294038536465a70660
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset creates Debug, Debugserver and Flash scripts
ensuring support in the ZephyrBinaryRunner mode.

Change-Id: Ib4f7820b1c6a045bd67cf4a031be99cf61e65eca
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.

ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
		RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/

Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.

This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.

Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.

Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.

Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS I2S on intel_s1000. Also, introduce a test to
validate I2S in ping-pong and normal modes.

Change-Id: Iea78e22cedc7724c1c2e821c68d7030cc0a65047
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I59091c465e84f1d6ba64433b7320182d83ff9589
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
patch add a hid test application which sends continues
reports to the host

Change-Id: I3a638caded629b502b4cfc6c7bdcba0b67428350
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A brief description about intel_s1000 and ways to connect,
flash, debug etc.

Change-Id: I459c64d8d9574bc3511da7f983d68e044cacc1d0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support to enable test application selectively based
on defconfig

Change-Id: I8111750ff099edd95ffa22c6e312999c801678ea
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I309bc50c6b575caa84fbc7ab98cc9890771b4274
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Change-Id: I9104f5230a4efbf1b6979e146e7ea73a76891947
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Add dts support for multilevel DW interrupt controller

Change-Id: Ia16d6870bd3a46fca933c906aedc6ba78ed5131a
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
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rgundi commented Apr 26, 2018

@lpereira , @mbolivar : I have incorporated your suggestions. Please review.

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nashif commented May 1, 2018

recheck

@nashif nashif merged commit 7be3236 into zephyrproject-rtos:master May 1, 2018
@rgundi rgundi deleted the S1000_migrate branch May 6, 2018 06:56
SebastianBoe added a commit to SebastianBoe/zephyr that referenced this pull request Sep 19, 2018
This re-applies a patch that was merged in pr zephyrproject-rtos#6989, but then
accidentally reverted in a bad merge conflict resolution in pr zephyrproject-rtos#6842.

The actual behaviour of CONIG_FP_SOFTABI has not been matching the
documenation. The Kconfig documentation states that floating point
instructions should be generated, but this Kconfig option has been
turning off floating point instructions instead.

This commit causes floating point instructions to be generated when
CONFIG_FP_SOFTABI is enabled, as was originally intended and
documented.

This commit can cause regressions if users have been relying on the
actual behaviour instead of the documented behaviour.

Kconfig documentation:

config FP_SOFTABI
	help
	  This option selects the Floating point ABI in which hardware
	  floating point instructions are generated but soft-float calling
	  conventions.

GCC documentation:

Specifying ‘soft’ causes GCC to generate output containing library
calls for floating-point operations. ‘softfp’ allows the generation of
code using hardware floating-point instructions, but still uses the
soft-float calling conventions. ‘hard’ allows generation of
floating-point instructions and uses FPU-specific calling conventions.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
nashif pushed a commit that referenced this pull request Sep 19, 2018
This re-applies a patch that was merged in pr #6989, but then
accidentally reverted in a bad merge conflict resolution in pr #6842.

The actual behaviour of CONIG_FP_SOFTABI has not been matching the
documenation. The Kconfig documentation states that floating point
instructions should be generated, but this Kconfig option has been
turning off floating point instructions instead.

This commit causes floating point instructions to be generated when
CONFIG_FP_SOFTABI is enabled, as was originally intended and
documented.

This commit can cause regressions if users have been relying on the
actual behaviour instead of the documented behaviour.

Kconfig documentation:

config FP_SOFTABI
	help
	  This option selects the Floating point ABI in which hardware
	  floating point instructions are generated but soft-float calling
	  conventions.

GCC documentation:

Specifying ‘soft’ causes GCC to generate output containing library
calls for floating-point operations. ‘softfp’ allows the generation of
code using hardware floating-point instructions, but still uses the
soft-float calling conventions. ‘hard’ allows generation of
floating-point instructions and uses FPU-specific calling conventions.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
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10 participants